Intel Pentium 4 User Manual

Platform Placement and Stack-Up Overview
R
34 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
3.1.2.1 Four-Layer Motherboard Routing Strategy
The routing strategy used on the 4-layer CRB is as follows:
• Hub interface routing
 Route hub interface signals across the middle of the two RIMM connectors on channel A
and then across to the ICH2.
 Breakout hub interface signals on top layer to allow 1.8V core and RAC MCH power to
be supplied to the MCH in the hub interface pin field on the bottom layer and power
plane.
• AGP routing
 Half of the signals are routed on the top layer referenced to V
DDQ
and the other half is
routed on the bottom referenced to GND.
• PCI routing
 PCI signals are routed in a T-topology. Signals are routed on the bottom of the board
from the ICH2 towards PCI connectors. When the traces reach the PCI connector, they
transition to the top layer and are routed horizontally, freeing up vertical routing channel
for clock, LAN, AC’97 and legacy IO routing from the SIO.
• System bus routing
 The MCH is placed below the processor socket for optimal power delivery to the
processor and MCH. System bus signals are routed around the processor. A ground flood
on the top layer and a V
CCP
flood on the bottom layer connect the OSCON and high
frequency capacitors together. The floods reduce power/GND plane inductance and
maximize capacitor efficiency.
 Half of the system bus signals are routed on the top layer referenced to V
CCP
and the other
half of the signals are routed on the bottom layer referenced to GND.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB