Intel Pentium 4

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Debug Port Routing Guidelines

Intel

Pentium

4 Processor / Intel

850 Chipset Family Platform Design Guide 239

13 Debug Port Routing Guidelines

In Pentium 4 processor in the 478-pin package based systems, the debug port should be

implemented as an on-board debug port.

Refer to the latest revision of the Pentium

4 Processor in the 478-pin Package Debug Port

Design Guide for details on the implementation of the debug port.

Main Page

Table of Contents3
Introduction17
Related Documentation18
Conventions and Terminology19
Table 1. Platform Conventions and Terminology19
System Overview21
- Intel ® Pentium ® 4 Processor in the 478-Pin Package21
- System Configurations23
- Figure 1.Typical System Configuration23
Platform Initiatives24
- Intel ® 850 Chipset24
- Platform Manageability27
PC '99/'01 Platform Compliance28
Component Quadrant Layout29
- Processor Component Quadrant Layout29
- Figure 2. Processor Socket Quadrant Layout29
- Intel ® 850/850E Chipset Component Quadrant Layout30
- Figure 3. Intel ® 850/850E Chipset Quadrant Layout30
- Figure 4. Intel ® ICH2 Quadrant Layout30
Platform Placement and Stack-Up Overview31
- Platform Component Placement31
- Motherboard Layer Stack-Up36
Platform Clock Routing Guidelines39
- Figure 11. Clocking Architecture Using the CK0040
- Figure 12. Processor BCLK Topology41
- Routing Guidelines for System Bus Clocks41
- Figure 13. Source Shunt Termination42
- Table 5. BCLK [1:0] Routing Guidelines43
- Figure 14. Clock Skew as Measured from Agent to Agent45
- Figure 15. Trace Spacing45
- BCLK[1:0] Frequency Select46
- CK00 to Rambus DRCG* (Reference Clocks)48
- Figure 18. Vddir and 3Vmref Routing48
- Routing Guidelines for Rambus RDRAM* Device Clocks48
- Intel ® MCH to Rambus DRCG* (Phase Aligning Clocks)49
- Routing Guidelines for 66 Mhz and 33 Mhz Clocks56
System Bus Routing61
- Table 10. System Bus Routing Summary for the Processor61
- Return Path62
- Figure 32. GTLREF Routing63
- GTLREF Layout and Routing Recommendations63
- Processor Configuration64
  - Topology and Routing64
- Routing Guidelines for Asynchronous GTL+ and Other Signals71
  - Table 13. Miscellaneous Signals (Signals that Are Not Data, Address, or Strobe)71
  - Topologies72
- Figure 48. THERMTRIP# Power down Sequence82
- Figure 49. Voltage Divider Network for Reference Voltage Generation82
- Intel ® MCH System Bus Interface82
- Figure 50. Pull-Down Circuit83
- Intel ® MCH System Bus I/O Decoupling Requirements83
- System Bus Routing Guidelines - Four-Layer Motherboard85
Memory Interface Routing89
- Rambus RDRAM* Device Routing Guidelines90
- Rambus Technology Routing Guidelines - Four-Layer Motherboard110
AGP Interface Routing113
- Table 25. AGP 2.0 Signal Groups113
- AGP Routing Guidelines114
- AGP Universal Retention Mechanism (RM)121
- Table 28. 3.3 V and 5 V Tolerant Signals During 1.5 V Operation121
- Figure 78. AGP Left Handed Retention Mechanism Drawing122
- Figure 79. AGP Left Handed Retention Mechanism Keep-Out Information123
- Table 29 List of Vendors for Retention Mechanism123
- AGP Routing Guidelines - Four-Layer Motherboard124
- Figure 80. Example AGP Routing (Top Layer)124
- Figure 81. Example AGP Routing (Bottom Layer)125
- Figure 82. Example VDDQ Plane on Layer 2126
Hub Interface Routing127
- Hub Interface Routing Guidelines127
- Figure 83. 8-Bit Hub Interface Routing Example127
- 8-Bit Hub Interface Routing Guidelines128
- Hub Interface Routing Guidelines - Four-Layer Motherboard131
- Figure 86. Example Hub Interface Breakout / 1.8 V MCH Fingers131
I/O Controller Hub 2133
- This Chapter Provides Information on the Intel 82801BA I/O Controller Hub 2 (ICH2) IDE Interface133
  - IDE Cable133
  - Cable Detection for Ultra ATA/66 and Ultra ATA/100134
  - Primary IDE Connector Requirements137
  - Figure 89. Connection Requirements for Primary IDE Connector137
  - Secondary IDE Connector Requirements138
  - Figure 90. Connection Requirements for Secondary IDE Connector138
- Communication and Networking Riser (CNR)139
  - CNR Placement139
  - Figure 91. CNR Interface139
- Intel ® AC'97140
  - Figure 92. Intel ® ICH2 AC'97 - Codec Connection140
  - Table 54. Intel140
  - Table 55. Intel140
  - Figure 93. Audio Codec141
  - Figure 94. Modem Codec141
  - Figure 95. Audio/Modem Codec141
  - Figure 96. Modem Codecs142
  - Figure 97. Audio and Modem Codecs142
  - Figure 98. Audio Codecs143
  - Figure 99. Audio and Audio/Modem Codecs143
  - AC'97 Audio Codec Detect Circuit and Configuration Options144
  - Table 33. Intel ® AC'97 SDIN Pull-Down Resistors144
  - Figure 100. CDC_DN_ENAB# Support Circuitry for a Single Codec Motherboard145
  - Figure 101. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade146
  - Figure 102. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / One-Codec on CNR146
  - Figure 103. CDC_DN_ENAB# Support for Two-Codecs on Motherboard / Two-Codecs on CNR147
  - Table 34. Signal Descriptions147
  - Valid Codec Configurations148
- USB Guidelines148
- Table 35. Codec Configurations148
- IOAPIC Design Recommendations149
- Figure 104. USB Data Signals149
- Smbus/Smlink Interface150
  - Figure 105. Smbus/Smlink Interface150
  - Smbus Architecture and Design Considerations151
- Pci153
  - Figure 108. Mixed Vcc_Suspend/Vcc_Core Architecture153
  - Figure 109. PCI Bus Layout Example153
  - Figure 110. Example PCI Power Planes on Layer 2154
  - PCI Routing - Four-Layer Motherboard154
  - Figure 111. Example PCI Routing on Layer 1155
  - Figure 112. Example PCI Routing on Layer 4156
- Rtc157
  - RTC Crystal157
  - Figure 113. External Circuitry for the Intel157
  - External Capacitors158
  - RTC Layout Considerations158
  - RTC External Battery Connection158
  - RTC External RTCRST Circuit159
  - Figure 114. Diode Circuit to Connect RTC External Battery159
  - RTC Routing Guidelines160
  - VBIAS DC Voltage and Noise Measurements160
  - Figure 115. RTCRST External Circuit for the Intel160
  - Power-Well Isolation Control161
  - Figure 116. RTC Power-Well Isolation Control161
  - Power Supply PS_ON Consideration162
- LAN Layout Guidelines162
  - Table 36. Integrated LAN Options162
  - Figure 117. Intel ® ICH2 / LAN Connect Section163
  - Table 37. LAN Design Guide Section Reference163
  - Intel ® ICH2 - LAN Interconnect Guidelines164
  - General LAN Routing Guidelines and Considerations167
  - Intel ® 82562EH Home/Pna* Guidelines172
  - Intel ® 82562ET / 82562EM Guidelines175
  - Figure 128. Intel ® 82562ET/EM Disable Circuit180
  - Intel ® 82562 ET/EM Disable Guidelines180
  - 82562ET / 82562EH Dual Footprint Guidelines181
  - Figure 129. Dual Footprint LAN Connect Interface181
  - Figure 130. Dual Footprint Analog Interface181
- Intel ® ICH2 Routing Guidelines - Four-Layer Motherboard183
- Figure 131. Example Intel ® ICH2 Top Layer Breakout Using Standard Size Vias183
- Figure 132. Example Intel ® ICH2 Bottom Layer Breakout Using Standard Size Vias184
- FWH Guidelines185
  - FWH Decoupling185
  - In Circuit FWH Programming185
  - FWH Vpp Design Guidelines185
  - Figure 133. FWH VPP Isolation Circuitry185
- Intel ® ICH2 Decoupling Recommendations186
- Glue Chip 4 (Intel ICH2 Glue Chip)186
- Table 42. Decoupling Capacitor Recommendation186
- SPKR Pin Consideration187
- Figure 134. SPKR Circuit187
- 1.8 V and 3.3 V Power Sequence Requirement188
- Figure 135. Example Power-On 3.3 V / 1.8 V Sequencing Circuit188
- PIRQ Routing189
- Figure 136. Example PCI IRQ Routing189
- Table 43. IOAPIC Interrupt Inputs 16 through 23 Usage189
Additional Design Considerations191
- Retention Mechanism Placement and Keepouts191
- Figure 137. RM Keepout Drawing 1192
- Figure 138. RM Keepout Drawing 2193
- Figure 139. Intel ® MCH Keepouts and RM Hole Locations194
- Power Header for Active Cooling Solutions195
- Table 44. Reference Solution Fan Power Header Pinout195
- Table 45. Boxed Processor Fan Power Header Pinout195
- Intel ® Pentium197
  - Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines197
- Power Requirements197
- Thermal Considerations220
- Simulation223
- Filter Specifications for VCCA, VCCIOPLL, and VSSA225
- Figure 168. Typical VCCIOPLL, VCCA and VSSA Power Distribution225
- Figure 169. Filter Recommendation226
- Figure 170. Example Component Placement for PLL Filter227
Power Distribution Guidelines229
- Definitions229
- Power Management229
- 1.8 V RAC Isolation Solution231
- Figure 172. Inductor-Capacitor Filter Circuit231
- Figure 173. Ferrite Bead Filter Circuit232
- Figure 174. Customer Reference Board Layout Example233
- Figure 175. Customer Reference Board Layout Example (Bottom - Layer 6)233
- Vterm/VDD Power Sequencing Requirement234
- Figure 176. Customer Reference Board Layout Example (Signal 2 - Layer 4)234
- Figure 177. 1.8 V and 2.5 V Power Sequence (Schottky Diode)234
- Intel ® 850 Chipset Power Sequencing Requirements235
- Figure 178. Desired Mode of Power Sequencing235
- Figure 179. Optional Mode of Power Sequencing235
- Intel ® ICH2 V5REF and Vcc3.3 Sequencing Requirement236
- Figure 180. V5REF Sequencing Circuit236
- CPU / CK00 Power Sequencing Requirement237
- Figure 181. CPU/CK00 Sequencing Circuit237
Debug Port Routing Guidelines239
Debug Tools Specifications241
- Logic Analyzer Interface (LAI)241
  - Mechanical Considerations241
  - Electrical Considerations241
Schematic Review Checklist243
- Processor Checklist (All Signals)243
- CK00 Clock Generator Checklist248
- Direct Rambus Clock Generator (DRCG1 and DRCG2) Checklist249
- Intel ® 850 Chipset Checklist251
- AGP Checklist253
- Rambus RIMM* Connector Checklist255
- Intel ® ICH2 Checklist259
Layout Review Checklist269
- Processor and System Bus269
- CK00 Routing Guidelines274
  - CK00 Clocking274
- RAMBUS Technology Routing Guidelines276
- AGP Guidelines282
- Bit Hub Interface285
  - Hub Decoupling285
- IDE Interface286
- Cnr286
- Intel ® AC'97286
- Usb287
- Intel ® ICH2 Decoupling287
- Rtc288
- LAN* Connect Interface288
- Miscellaneous289
Appendix A: Reference Schematics291

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