Intel Pentium 4 User Manual

System Bus Routing
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Intel
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Pentium
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4 Processor / Intel
®
850 Chipset Family Platform Design Guide 61
5 System Bus Routing
Table 10 summarizes the layout recommendations the processor configurations and expands on
specific design issues and their recommendations.
Table 10. System Bus Routing Summary for the Processor
Parameter Processor Routing Guidelines
Line to line spacing Data groups, address groups and control signals should be routed with 7 mil
traces and 13 mil spacing between traces.
Data Line lengths (a)
(agent to agent spacing)
for 82850 chipset
platforms
2 – 10 inches from pin to pin
Data signals of the same source synchronous group should be routed to the
same pad-to-pad length within ±100 mils of the median of the associated
strobes. Tighter tolerances for length matching will result in greater timing
margin for the system bus. The pad is defined as the attach point of the
silicon die to the package substrate. Signals in each source synchronous
group should be referenced to VSS. Signals within the same group may be
routed on different layers provided they are referenced to VSS and the layers
are of the same configuration (all stripline or all microstrip).
Data Line lengths (b)
(agent to agent spacing)
for 82850E chipset
platforms
2 – 8 inches from pin to pin
Data signals of the same source synchronous group should be routed to the
same pad-to-pad length within ±100 mils of the median of the associated
strobes. Tighter tolerances for length matching will result in greater timing
margin for the system bus. The pad is defined as the attach point of the
silicon die to the package substrate. Signals in each source synchronous
group should be referenced to VSS. Signals within the same group may be
routed on different layers provided they are referenced to VSS and the layers
are of the same configuration (all stripline or all microstrip).
DSTBn/p[3:0]# A data strobe and its complement should be routed within ±25 mils of the
same pad-to-pad length. The pad is defined as the attach point of the silicon
die to the package substrate.
DSTBn/p# should be referenced to VSS.
Address line lengths
(agent to agent spacing)
2 – 10 inches from pin to pin
Address signals of the same source synchronous group should be routed to
the same pad-to-pad length within ±200 mils of the associated strobe. Tighter
tolerances for length matching will result in greater timing margin for the
system bus. The pad is defined as the attach point of the silicon die to the
package substrate. A layer transition may occur if the reference plane
remains the same (VSS) and the layers are all of the same configuration (all
stripline or all microstrip).
ADSTBn/p[1:0]# 2 – 10 inches from pin to pin
Address signals of the same source synchronous group should be routed to
the same pad-to-pad length within ±200 mils of the associated strobe. Tighter
tolerances for length matching will result in greater timing margin for the
system bus. The pad is defined as the attach point of the silicon die to the
package substrate. A layer transition may occur if the reference plane
remains the same (VSS) and the layers are all of the same configuration (all
stripline or all microstrip).

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB