Intel Pentium 4 User Manual

I/O Controller Hub 2
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 151
Note: Intel does not support external access of the ICH2’s Integrated LAN Controller via the SMLink
interface. Also, Intel does not support access of the ICH2’s SMBus Slave Interface by the ICH2’s
SMBUS Host Controller.
Refer to the Intel
®
82801BA I/O Controller Hub 2 (ICH2) and Intel
®
82801BAM I/O Controller
Hub 2 Mobile (ICH2-M) Datasheet for full functionality descriptions of the SMLink and SMBus
interface.
9.6.1 SMBus Architecture and Design Considerations
9.6.1.1 SMBus Design Considerations
There are several possibilities for designing a SMBus using the ICH2. Designs can be grouped
into three major categories based on the power supply source for the SMBus microcontrollers.
This includes two unified designs, where all devices are powered by either VCC_Core or
VCC_Suspend, and a mixed design where some devices are powered by each of the two supplies.
Primary considerations in choosing a design are based on:
• Are there devices that must run in STR?
• Amount of VCC_Suspend current available, i.e. minimizing load of VCC_Suspend
9.6.1.2 General Design Issues / Notes
Regardless of the architecture used, there are some general considerations.
• The pull-up resistor size for the SMBus data and clock signals is dependent on the number of
devices present on the bus. A typical value is 8.2k ohms. This should prevent the SMBus
signals from floating, which could cause leakage in the ICH2 and other devices.
• RIMM modules have a separate power source from the RDRAM device array for the SPD
device. If this SPD device needs to operate in STR, then it should be connected to the
VCC_Suspend supply.
• The ICH2 does not run SMBus cycles while in STR.
• SMBus devices that can operate in STR must be powered by the VCC_Suspend supply.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB