Intel Pentium 4 User Manual

Platform Clock Routing Guidelines
R
48 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
4.3 Routing Guidelines for Rambus RDRAM* Device
Clocks
The CK00 clock synthesizer provides two 3.3 V clock reference outputs [3Vmref and 3Vmref#]
for the Direct Rambus* Clock Generator (DRCG* device). Two DRCG devices are required in an
850 chipset dual-Direct RDRAM channel interface. Some clock vendors may also have a DMCG
(Direct Multiple Clock Generator) component that combines the function of two DRCG devices
into one part. These DMCG components may be used as a cost-reduction opportunity with
appropriate validation.
The DRCG device reference clock operates at one-half the processor clock frequency. The
reference clocks are inputs into the DRCG devices and are used to generate the RDRAM device
“Clock to Master” differential pair (CTM, CTM#) clocks on each Direct RDRAM channel.
In addition, the DRCG uses phase information provided by the MCH via the RCLKOUT and
HCLKOUT phase aligning signals.
For an 82850E/PC1066 RDRAM technology platform, the DRCG devices should be 533 MHz
capable.
4.3.1 CK00 to Rambus DRCG* (Reference Clocks)
The 3VMRef clock output must be routed as shown in Figure 18. Note that the VddIR power pin
on the DRCG can be connected directly to 3.3 V near the DRCG if the 3.3 V plane extends near
the DRCG. However, if a 3.3 V trace must be used, it should originate at the clock synthesizer and
be routed as shown in Figure 18. The maximum routing length for the 3VMRef and 3VMRef#
signals is 8 inches.
Note: The following recommendations assume routing of the reference clocks as microstrip traces.
Figure 18. VddIR and 3VMRef Routing
Ground
Ground/Power Plane
6 mils
4.5 mils
6 mils
VddiR
6 mils
6 mils
Ground
6 mils
6 mils
3VMRef
6 mils
6 mils
Ground
6 mils
VddIR_3VMRef_route
NOTE: 3VMRef# should be routed in a similar manner as 3VMRef.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB