Intel Pentium 4 User Manual

Platform Clock Routing Guidelines
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 49
4.3.2 Intel
®
MCH to Rambus DRCG* (Phase Aligning Clocks)
The RCLKOUT and HCLKOUT signals from the MCH should be routed to the SYNCLKN and
PCLKM signals on the DRCG, respectively, as shown in Figure 19. Note that the VddiPD power
pin on the DRCG can be connected directly to 1.8 V near the DRCG if the 1.8 V plane extends
near the DRCG. However, if a 1.8 V trace must be used, it should originate at the CK00 clock
synthesizer and be routed as shown with respect to RCLKOUT and HCLKOUT.
The maximum length for RCLKOUT and HCLKOUT is 6 inches. Additionally, these signals must
be length matched within 50 mils. These signals should be routed on the same layer. If these
signals must switch layers, then BOTH signals should change layers together.
If the VddIPD pin is connected to the 1.8 V plane using a via (i.e., trace is not run from the CK00
clock synthesizers), then HCLKOUT and RCLKOUT must still be routed as shown below and
ground isolated.
Note: The following recommendations assume routing of the phase alignment clocks on microstrip.
Figure 19. Intel
®
MCH to Rambus DRCG* Routing
Ground
Ground/Power Pane
6 mils
6 mils
VddiPD
5 mils
6 mils
Ground
6 mils
6 mils
Rclkout
6 mils
12 mils
Hclkout
6 mils
6 mils
Ground
6 mils
mch-drcg_route
6 mils
NOTE: The signals Rclkout and Pclkout are channel specific, and their exact names are CHx_RCLKOUT and
CHx_PCLKOUT, where x is the channel, either A or B. Consult the Intel
®
850 Chipset Family:
82850/82850E Memory Controller Hub (MCH) Datasheet t for more information.
4.3.3 Rambus DRCG* to Direct Rambus Channels (400 MHz
Clocks)
The 400 MHz RDRAM device clock signals (CTM/CTM# and CFM/CFM#) are high-speed,
impedance matched transmission lines that require strict routing recommendations to insure that
the memory timings are met. The following RDRAM device clock recommendations should be
strictly followed. Any deviations from the recommendations should be properly simulated.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB