System Bus Routing
R
64 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
5.3 Processor Configuration
Both recommendations and considerations are described in this section.
For proper operation of the processor and the Intel 850 chipset, it is necessary that the system
designer meet the timing and voltage specifications of each component. The following
recommendations are Intel’s best guidelines based on extensive simulation and experimentation
that make assumptions that may be different than an OEM's system design. The most accurate way
to understand the signal integrity and timing of the system bus in your platform is by performing a
comprehensive simulation analysis. It is conceivable that adjustments to trace impedance, line
length, termination impedance, board stack-up and other parameters can be made that improve
system performance.
A schematic of the processor topology is shown in Figure 33. The trace impedance should be
50 Ω
±15%. The traces should maintain a greater than three to one edge-to-edge spacing versus
trace to reference plane height ratio. Simulations performed at Intel have assumed, for nominal
conditions, a 7 mil wide trace and 13 mil edge-to-edge spacing. As the traces pass through the pin
fields this requirement may not be achievable. In these areas where the 7 mil width and 13 mil
spacing is not possible, 7 mil traces with 5 mil spacing is acceptable.
Refer to the processor datasheet for a system bus signal list, signal types and definitions.
5.3.1 Topology and Routing
Table 11. Source Synchronous Signal Groups and the Associated Strobes
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB0#
A[32:17]# ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
Design recommendations will be presented first followed by design considerations.
To Next Page
Loading...
Need help?
General
