Intel Pentium 4

I/O Controller Hub 2
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 137
9.1.3 Primary IDE Connector Requirements
The 10 kΩ resistor to ground on the PDIAG/CBLID signal is now required on both the Primary
and Secondary Connectors. This change is to prevent the GPI pin from floating if a device is not
present on either IDE interface.
Figure 89. Connection Requirements for Primary IDE Connector
IDE_primary_conn_require
CSEL
* Due to ringing, PCIRST# must be buffered.
3.3 V
3.3 V
4.7 k
Ω 8.2–10 kΩ
10 kΩ
PDD[15:0]
PDA[2:0]
PDCS[3,1]#
PDIOR#
PDIOW#
PDDREQ
PDDACK#
PIORDY (PRDSTB / PWDMARDY#)
PDIAG / CBLID
IRQ14
GPIOx
Primary IDE Connector
ICH2
PCIRST# *
• 22 Ω – 47 Ω series resistors are required on RESET#. The correct value should be determined
for each unique motherboard design, based on signal quality.
• An 8.2 kΩ to 10 kΩ pull-up resistor is required on IRQ14 and IRQ15 to VCC3_3.
• A 4.7 kΩ pull-up resistor to VCC3_3 is required on PIORDY and SIORDY.
• Series resistors can be placed on the control and data line to improve signal quality. The
resistors are place as close to the connector as possible. Values are determined for each
unique motherboard design.