Intel Pentium 4 User Manual

System Bus Routing
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 63
5.2 GTLREF Layout and Routing Recommendations
There are four AGTL+ GTLREF pins on the processor that are used to set the reference voltage
level for the AGTL+ signals (GTLREF). Because all of these pins are connected inside the
processor package, the GTLREF voltage only needs to be supplied to one of the four pins. The
other three pins can be left unconnected.
Figure 32. GTLREF Routing
49.9 Ω 1%,
Vref_Route
TLine
100 Ω,1%
1 uF
220 pF
L1 = 1.5" max
Pin
VCC_CPU
• The processor must have one dedicated voltage divider.
• Decouple the voltage divider with a 1 µF capacitor.
• Keep the voltage divider within 1.5 inches of the GTLREF pin
• Decouple the pin with a high frequency capacitor (such as a 220 pF 603) as close to the
pin as possible
• Keep signal routing at least 10 mils separated from the GTLREF routes. Use a minimum
of a 7 mil trace for routing.
• Do not allow signal lines to use the GTLREF routing as part of their return path (i.e., do
not allow the GTLREF routing to create splits or discontinuities in the reference planes of
the system bus signals.)

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB