Intel Pentium 4 User Manual

Introduction
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 27
1.4.3 Platform Manageability
The Intel 850 chipset platform integrates several functions designed to manage the system and
lower the total cost of ownership (TCO) of the system. These system management functions are
designed to report errors, diagnose the system and recover from system lockups without the aid of
an external micro-controller.
Interrupt Controller: The interrupt capabilities of the ICH2 in an Intel 850 chipset-based platform
expands support for up to 8 PCI interrupt pins and PCI 2.2 Message-Based Interrupts. In addition,
the ICH2 supports system bus interrupt delivery.
TCO Timer: The ICH2 integrates a programmable TCO timer. This timer is used to detect system
locks. The first expiration of the timer generates an SMI# which the system can use to recover
from a software lock. The second expiration of the timer causes a system reset to recover from a
hardware lock.
Processor Present Indicator: The ICH2 looks for the processor to fetch the first instruction after
reset. If the processor does not fetch the first instruction the ICH2 has the ability to blink a GPIO
and reboot the system at the lowest frequency multiplier.
ECC Error Reporting: The MCH has the ability to send one of several messages to the ICH2
when an ECC error is detected. The MCH can tell the ICH2 to generate either an SMI#, SCI, or
SERR# interrupt.
Function Disable: The ICH2 provides the ability to disable the following functions: AC’97
Modem, AC’97 Audio, IDE, USB or SMBus. Once disabled, these functions no longer decode
I/O, memory, or PCI configuration space. Also, no interrupts or power management events are
generated from the disabled functions.
Intruder Detect: The ICH2 provides an input signal, INTRUDER#, that can be attached to a
switch that is activated by the system case being opened. The ICH2 can be programmed to
generate an SMI# or TCO interrupt due to an active INTRUDER# signal.
SMBus: The ICH2 integrates a SMBus controller. The SMBus provides an interface to manage
peripherals such as serial presence detection (SPD) on RIMM modules and thermal probes. A
slave interface is also provided to enable additional platform manageability. This interface allows
and external microcontroller to access system resources, as well as external system devices the
ability to check the system power state, watchdog timer, and system status bits and generate a
system reset and other platform messages.
Alert-On-LAN*: The ICH2 supports Alert-On-LAN*. In response to a TCO event (intruder detect,
thermal event, processor not booting) the ICH2 will send a hard-coded message over the SMLink.
Refer to the Wired for Management (WfM) Design Guide at http://www.intel.com/ial/wfm/design/
for additional information.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB