Intel Pentium 4 User Manual

System Bus Routing
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Intel
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Pentium
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4 Processor / Intel
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850 Chipset Family Platform Design Guide 65
5.3.1.1 Design Recommendations
Below are the design recommendations for the data, address, strobes, and common clock signals.
For the following discussion, the pad is defined as the attach point of the silicon pad to the
package substrate.
Data
The pin to pin distance from the processor to the chipset should be between 2.0 to 10 inches (i.e.,
2.0 inches < L1 < 10 inches). Data signals of the same source synchronous group should be routed
to the same pad to pad length within ±100 mils of the associated strobes. As a result, additional
trace will be added to some data nets on the system board in order for all trace lengths within the
same data group to be the same length (±100 mils) from the pad of the processor to the pad of the
chipset. This length compensation will result in minimizing the source synchronous skew that
exists on the system bus. Without the length compensation the flight times between a data signal
and its strobe will be different, which results in an inequity between the setup and hold times.
Equation 1. Calculations to determine the package delta addition to motherboard length for
UP systems
)cs_pkglen(cs_pkglen)cpu_pkglenn(cpu_pkgledelta
strobenet*strobenetnet,strobe
−+−=
NOTE: Strobe package length is the average of the strobe pair.
Address
Address signals follow the same rules as data signals except they should be routed to the same pad
to pad length within ±200mils of the associated strobes. Address signals may change layers if the
reference plane remains VSS and as long as the layers for a given group are all of the same
configuration (all stripline or all microstrip).
Data Strobes
A strobe and its complement (xSTBp/n#) should be routed to ±25 mils of the same length. It is
recommended to simulate skew in order to determine the length that best centers the strobe for a
given system.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB