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Intel Pentium 4 User Manual

Intel Pentium 4
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Layout Review Checklist
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 279
16.3.3 V
term
Layout
Recommendations Reason/Impact
Solid V
TERM
island is on top routing layer; do
not split this plane
Ground island (for ground side of V
TERM
capacitors) is on top routing layer
Termination resistors connect directly to the
V
TERM
island on the top routing layer
(without vias)
Resistor packs are acceptable; however,
discrete resistors are recommended for
increase margin and control.
Refer to Section 6.1.3.
Decoupling capacitors connect to top layer
V
TERM
island and top routing layer ground
island directly.
Use at least 2 vias per decoupling capacitor
in the top layer ground island.
Use 2x100 µF Tantalum capacitors to
decouple V
TERM
.
Refer to Section 6.1.3.
Hi-frequency decoupling capacitors must be
spread-out across the termination island so
that all termination resistors are near high
frequency capacitors.
Refer to Section 6.1.3.
100 µF Tantalum capacitor should be at
each end of the V
TERM
island.
Refer to Section 6.1.3.
100 µF Tantalum capacitors must be
connected to the V
TERM
island directly
Refer to Section 6.1.3.
100 µF Tantalum capacitors must have at
least 2 vias/capacitor to ground.
V
TERM
island should be at least 50 mils wide Refer to Section 6.1.3

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Intel Pentium 4 Specifications

General IconGeneral
Architecturex86
Core Count1
MicroarchitectureNetBurst
ManufacturerIntel
Core NamesWillamette, Northwood, Prescott, Cedar Mill
Virtualization TechnologyNo
Release DateNovember 20, 2000
Clock Speed1.3 GHz to 3.8 GHz
FSB Speed400 MHz to 1066 MHz
SocketSocket 423, Socket 478, LGA 775
Introduced2000
Product LinePentium
Front Side Bus400 MHz to 1066 MHz
Hyper-ThreadingYes (Prescott and later)
64-bit SupportYes (Prescott and later)
Instruction SetMMX, SSE, SSE2, SSE3
Discontinued2008
Process Technology180 nm, 130 nm, 90 nm, 65 nm
L2 Cache256 KB, 512 KB, 1 MB, 2 MB
Lithography180 nm, 130 nm, 90 nm, 65 nm
L1 Cache8 KB

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