Signal Description
R
Intel
®
82925X/82925XE MCH Datasheet 21
2 Signal Description
This chapter provides a detailed description of MCH signals. The signals are arranged in
functional groups according to their associated interface. The states of all of the signals during
reset are provided in the Section 2.9.
The following notations are used to describe the signal type:
I Input pin
O Output pin
I/O Bi-directional input/output pin
GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for
complete details. The MCH integrates GTL+ termination resistors, and supports
VTT
of from 0.83 V to 1.65 V (including guardbanding).
PCIE PCI-Express interface signals. These signals are compatible with PCI Express
1.0 Signaling Environment AC Specifications and are AC coupled. The buffers
are not 3.3 V tolerant. Differential voltage specification
= (|D+ - D-|) * 2 = 1.2 V maximum Single-ended maximum = 1.5 V.
Single-ended minimum = 0 V.
DMI Direct Media Interface signals. These signals are compatible with PCI Express
1.0 Signaling Environment AC Specifications, but are DC coupled. The buffers
are not 3.3 V tolerant. Differential voltage specification
= (|D+ - D-|) * 2 = 1.2 V maximum. Single-ended maximum = 1.5 V.
Single-ended minimum = 0 V.
CMOS CMOS buffers. 1.5 V tolerant.
COD CMOS Open Drain buffers. 2.5 V tolerant.
HVCMOS High Voltage CMOS buffers. 2.5 V tolerant.
HVIN High Voltage CMOS input-only buffers. 3.3 V tolerant.
SSTL-1.8 Stub Series Termination Logic. These are 1.8 V output capable buffers; 1.8 V
tolerant. An I/O voltage of 1.9 V is needed for D DR2 533 MHz CL3-3-3.
A Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
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