Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

Host Bridge/DRAM Controller Registers (D0:F0)
R
68 Intel
®
82925X/82925XE MCH Datasheet
4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0)
PCI Device: 0
Address Offset: 96h
Default Value: 00h
Access: R/W
Size: 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h–
0EFFFFh.
Bit Access &
Default
Description
7:6 Reserved
5:4 R/W
00b
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:2 Reserved
1:0 R/W
00b
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English