Host Bridge/DRAM Controller Registers (D0:F0)
R
74 Intel
®
82925X/82925XE MCH Datasheet
4.1.32 ERRCMD—Error Command (D0:F0)
PCI Device: 0
Address Offset: CAh
Default Value: 0000h
Access: R/W
Size: 16 bits
This register controls the MCH responses to various system errors. Since the MCH does not have
an SERR# signal, SERR messages are passed from the MCH to the Intel ICH6 over DMI. When a
bit in this register is set, a SERR message will be generated on DMI when the corresponding flag
is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for
Device 0 via the PCI Command register.
Bit Access &
Default
Description
15:12 Reserved
11 R/W
0b
SERR on MCH Thermal Sensor Event (TSESERR)
1 = The MCH generates a DMI SERR special cycle when bit 11 of the ERRSTS
is set. The SERR must not be enabled at the same time as the SMI for the
same thermal sensor event.
0 = Reporting of this condition via SERR messaging is disabled.
10 Reserved
9 R/W
0b
SERR on LOCK to non-DRAM Memory (LCKERR)
1 = The MCH will generate a DMI SERR special cycle whenever a processor lock
cycle is detected that does not hit DRAM.
0 = Reporting of this condition via SERR messaging is disabled.
8 R/W
0b
SERR on DRAM Refresh Timeout (DRTOERR)
1 = The MCH generates a DMI SERR special cycle when a DRAM Refresh
timeout occurs.
0 = Reporting of this condition via SERR messaging is disabled.
7:2 Reserved
1 R/W
0b
82925X MCH
SERR Multiple-Bit DRAM ECC Error (DMERR)
1 = The MCH generates a SERR message over DMI when it detects a multiple-bit
error reported by the DRAM controller.
0 = Reporting of this condition via SERR messaging is disabled. For systems not
supporting ECC, this bit must be disabled.
82925XE MCH
Reserved
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