Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 153
8.1.56 ESD—Element Self Description (D1:F0)
PCI Device: 1
Address Offset: 144h
Default Value: 02000100h
Access: RO, R/WO
Size: 32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit Access &
Default
Description
31:24 RO
02h
Port Number: This field specifies the port number associated with this element
with respect to the component that contains this element. The egress port of the
component to provide arbitration to this Root Complex Element uses this port
number value.
23:16 R/WO
00h
Component ID: This field indicates the physical component that contains this
Root Complex Element. Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:8 RO
01h
Number of Link Entries: This field indicates the number of link entries following
the Element Self Description. This field reports 1 (to Egress port only as peer-to-
peer capabilities in this topology are not reported).
7:4 Reserved
3:0 RO
0h
Element Type: This field indicates the type of the Root Complex Element.
0h = root port.
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