System Address Map
R
168 Intel
®
82925X/82925XE MCH Datasheet
9.4.2 SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and
may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to
system main memory, or to any “PCI” devices (including DMI, PCI Express, and graphics
devices). This is a BIOS responsibility.
• Both D_OPEN and D_CLOSE capability must not be enabled at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as
available main memory. This is a BIOS responsibility.
• Any address translated through the GMADR TLB must not target main memory from
A_0000h–F_FFFFh.
9.4.3 SMM Space Combinations
When High SMM is enabled, the Compatible SMM space is effectively disabled. Processor
originated accesses to the Compatible SMM space are forwarded to PCI Express if this VGA
capability is enabled; otherwise, they are forwarded to the DMI. PCI Express and DMI originated
accesses are never allowed to access SMM space.
Table 9-5. SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0 X X Disable Disable Disable
1 0 0 Enable Disable Disable
1 0 1 Enable Disable Enable
1 1 0 Disabled Enable Disable
1 1 1 Disabled Enable Enable
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