Host Bridge/DRAM Controller Registers (D0:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 51
4.1.5 RID—Revision Identification (D0:F0)
PCI Device: 0
Address Offset: 08h
Default Value: See table below
Access: RO
Size: 8 bits
This register contains the revision number of the MCH Device 0.
Bit Access &
Default
Description
7:0 RO
00h
Revision Identification Number (RID): This is an 8-bit value that indicates the
revision identification number for the MCH Device 0. See Intel
®
925X/925XE
Express Chipset Specification Update for the value of the Revision Identification
Register.
4.1.6 CC—Class Code (D0:F0)
PCI Device: 0
Address Offset: 09h
Default Value: 060000h
Access: RO
Size: 24 bits
This register identifies the basic function of the device, a more specific sub-class, and a register-
specific programming interface.
Bit Access &
Default
Description
23:16 RO
06h
Base Class Code (BCC): This is an 8-bit value that indicates the base class
code for the MCH.
06h = Bridge device.
15:8 RO
00h
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of
Bridge into which the MCH falls.
00h = Host Bridge.
7:0 RO
00h
Programming Interface (PI): This is an 8-bit value that indicates the
programming interface of this device. This value does not specify a particular
register set layout and provides no practical use for this device.