Host Bridge/DRAM Controller Registers (D0:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 45
4 Host Bridge/DRAM Controller
Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Warning: Address locations that are not listed are considered Reserved registers locations. Reads to
Reserved registers may return non-zero values. Writes to reserved locations may cause system
failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in
this component are not included in this document. The reserved/unimplemented space in the PCI
configuration header space is not documented as such in this summary.
Table 4-1. Device 0 Function 0 Register Address Map Summary
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00h–01h VID Vendor Identification 8086h RO
02h–03h DID Device Identification 2580h RO
04h–05h PCICMD PCI Command 0006h RO, R/W
06h–07h PCISTS PCI Status 0090h RO,
R/W/C
08h RID Revision Identification See Register
Description
RO
09h–0Bh CC Class Code 060000h RO
0Ch — Reserved — —
0Dh MLT Master Latency Timer 00h RO
0Eh HDR Header Type 00h RO
0Fh–2Bh — Reserved — —
2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/W/O
2Eh–2Fh SID Subsystem Identification 0000h R/W/O
30h–33h — Reserved — —
34h CAPPTR Capabilities Pointer E0h RO
35h–3Fh — Reserved — —
40h–43h EPBAR Egress Port Base Address 00000000h RO
44h–47h MCHBAR MCH Memory Mapped Register Range Base
Address
00000000h R/W
48h–4Bh PCIEXBAR PCI Express* Register Range Base Address E0000000h R/W
4Ch–4Fh DMIBAR Root Complex Register Range Base Address 00000000h R/W
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