System Address Map
R
Intel
®
82925X/82925XE MCH Datasheet 157
9 System Address Map
The MCH supports 4 GB of addressable memory space (see Figure 9-1) and 64 KB+3 bytes of
addressable I/O space. A programmable memory address space under the 1-MB region is divided
into regions that can be individually controlled with programmable attributes such as disable,
read/write, write only, or read only. This section focuses on how the memory space is partitioned
and what the separate memory regions are used for. I/O address space has simpler mapping and is
explained near the end of this section.
Addressing of memory ranges larger than 4 GB is not supported. The HREQ[4:3] FSB pins are
decoded to determine whether the access is above or below 4 GB.
The MCH does not support the PCI Dual Address Cycle (DAC) Mechanism, PCI Express
64-bit prefetchable memory transactions, or any other addressing mechanism that allows
addressing of greater than 4 GB on either the DMI or PCI Express interface. The MCH does not
limit system memory space in hardware. There is no hardware lock to stop someone from
inserting more memory than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the
DMI. The exception to this rule is VGA ranges that may be mapped to PCI Express or DMI. In
the absence of more specific references, cycle descriptions referencing PCI should be interpreted
as the DMI/PCI, while cycle descriptions referencing PCI Express are related to the PCI Express
bus. The MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low
Usable DRAM). The TOLUD register is set to the appropriate value by BIOS.
• Device 0
⎯ EPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous channel
using time based weighted round robin arbitration. (4-KB window)
⎯ MCHBAR – Memory mapped range for internal MCH registers. For example, memory
buffer register controls. (16-KB window)
⎯ PCIEXBAR – Flat memory-mapped address space to access device configuration
registers. This mechanism can be used to access PCI configuration space (0h–FFh) and
Extended configuration space (100h–FFFh) for PCI Express devices. This enhanced
configuration access mechanism is defined in the PCI Express specification. (256-MB
window)
⎯ DMIBAR –This window is used to access registers associated with the MCH/ICH6
(DMI) register memory range. (4-KB window)
⎯ IFPBAR – Any write to this window will trigger a flush of the MCH’s Global Write
Buffer to let software guarantee coherency between writes from an isochronous agent
and writes from the processor (4-KB window).
• Device 1: Function 0:
⎯ MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
⎯ PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
⎯ IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
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