Testability
R
222 Intel
®
82925X/82925XE MCH Datasheet
13.2 XOR Test Mode Initialization
XOR test mode can be entered by pulling reserved ballout RSV (located at F15) and MTYPE low
through the de-assertion of external reset (RSTIN#). It is recommended that customers use the
following sequence.
After power up, hold PWROK, PCIRST#, and reserved ballout RSV (located at F15) and
MTYPE low and start external clocks. After 20 cycles, pull PWROK high. After 15 clocks, de-
assert PCIRST# (pull it high). Release reserved ballout RSV (located at F15) and MTYPE. No
external drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains.
13.3 XOR Chain Definition
The 82925X/82925XE MCH has 10 XOR chains. The XOR chain outputs are driven out on the
following output pins. During full-width testing, XOR chain outputs will be visible on both pins.
For example xor_out0 will be visible on BSEL2.
Table 13-2. XOR Chain Outputs
XOR Chain Output Pins Coordinate Location
xor_out0 BSEL2 D17
xor_out1 RSV M16
xor_out2 RSV F15
xor_out3 MTYPE C15
xor_out4 RSV A16
xor_out5 RSV B15
xor_out6 RSV C14
xor_out7 RSV K15
xor_out8 BSEL1 E15
xor_out9 BSEL0 H16
13.4 XOR Chains
The following tables show the XOR chains. The last section in this chapter has a pin exclusion
list. The chain files are golden, if there is a pin missing from the chain files and exclusion list, it
should be added to the exclusion list.
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