Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 117
8.1.7 CL1—Cache Line Size (D1:F0)
PCI Device: 1
Address Offset: 0Ch
Default Value: 00h
Access: R/W
Size: 8 bits
Bit Access &
Default
Description
7:0 R/W
00h
Cache Line Size (Scratch pad): This field is implemented by PCI Express*
devices as a read/write field for legacy compatibility purposes but have no impact
on any PCI Express device functionality.
8.1.8 HDR1—Header Type (D1:F0)
PCI Device: 1
Address Offset: 0Eh
Default Value: 01h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit Access &
Default
Description
7:0 RO
01h
Header Type Register (HDR): This field returns 01h to indicate that this is a
single function device with bridge header layout.
8.1.9 PBUSN1—Primary Bus Number (D1:F0)
PCI Device: 1
Address Offset: 18h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus 0.
Bit Access &
Default
Description
7:0 RO
00h
Primary Bus Number (BUSN): Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device 1
is an internal device and its primary bus is always 0, these bits are read only and
are hardwired to 0.

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English