Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 121
8.1.15 MBASE1—Memory Base Address (D1:F0)
PCI Device: 1
Address Offset: 20h
Default Value: FFF0h
Access: R/W
Size: 16 bits
This register controls the processor to PCI Express Graphics non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. The configuration software must initialize this register. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
Bit Access &
Default
Description
15:4 R/W
FFFh
Memory Address Base (MBASE): This field corresponds to A[31:20] of the
lower limit of the memory range that will be passed to PCI Express*.
3:0 Reserved
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