Host Bridge/DRAM Controller Registers (D0:F0)
R
52 Intel
®
82925X/82925XE MCH Datasheet
4.1.7 MLT—Master Latency Timer (D0:F0)
PCI Device: 0
Address Offset: 0Dh
Default Value: 00h
Access: RO
Size: 8 bits
Device 0 in the MCH is not a PCI master. Therefore this register is not implemented.
Bit Access &
Default
Description
7:0 Reserved
4.1.8 HDR—Header Type (D0:F0)
PCI Device: 0
Address Offset: 0Eh
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit Access &
Default
Description
7:0 RO
00h
PCI Header (HDR): This field always returns 0 to indicate that the MCH is a
single function device with standard header layout.
4.1.9 SVID—Subsystem Vendor Identification (D0:F0)
PCI Device: 0
Address Offset: 2Ch
Default Value: 0000h
Access: R/WO
Size: 16 bits
This value is used to identify the vendor of the subsystem.
Bit Access &
Default
Description
15:0 R/WO
0000h
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-
up to indicate the vendor of the system board. After it has been written once, it
becomes read only.
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