Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU - Figure 1-1. Intel 925 X925 XE Express Chipset System Block Diagram Example

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Introduction

14 Intel

82925X/82925XE MCH Datasheet

Figure 1-1. Intel

925X/925XE Express Chipset System Block Diagram Example

Intel

82925X MCH/

Intel

82925XE MCH

Intel

Pentium

Processor

DDR2

Channel A

200/266 MHz FSB

(800/1066 MT/s)

DMI Interface

Sys_Blk_P

Channel B

Graphics

Card

PCI Express

x16 Graphics

Intel

925X/925XE Express Chipset

System Memory

Display

Intel

ICH6 Family

USB 2.0

8 ports, 480 Mb/s

4 SATA Ports

150 MB/s

IDE

SIO

Flash

BIOS

PCI Bus

Seven PCI Masters

AC '97/Intel

High

Definition Audio

CODECs

LPC

Interface

Power Management

Clock Generation

System

Management (TCO)

LAN Connect/ASF

SMBus 2.0/I

GPIO

PCI Express* x1

Intel

PCI Express

Gigabit Ethernet

Note: 266 MHz (1066 MT/s) FSB is for 82925XE MCH only

Main Page

Table of Contents3
Revision History11
Introduction13
Figure 1-1. Intel 925X/925XE Express Chipset System Block Diagram Example14
Terminology15
Reference Documents16
MCH Overview16
- Host Interface16
- System Memory Interface17
- Direct Media Interface (DMI)18
- PCI Express* Graphics Interface18
- System Interrupts19
- MCH Clocking20
- Power Management20
Signal Description21
Figure 2-1. Intel ® 82925X/82925XE MCH Signal Interface Diagram22
Host Interface Signals23
Figure 2-1. Intel26
DDR2 DRAM Channel a Interface26
DDR2 DRAM Channel B Interface27
DDR2 DRAM Reference and Compensation28
PCI Express* X16 Graphics Port Signals28
Clocks, Reset, and Miscellaneous29
Direct Media Interface (DMI)29
Power and Ground30
Reset States and Pull-Up/Pull-Downs30
Table 2-1. Host Interface Reset and S3 States31
Table 2-2. System Memory Reset and S3 States32
Table 2-3. PCI Express* Graphics X16 Port Reset and S3 States33
Table 2-4. DMI Reset and S3 States33
Table 2-5. Clocking Reset and S3 States34
Table 2-6. Miscellaneous Reset and S3 States34
Register Description35
Register Terminology35
Figure 3-1. Conceptual Intel37
Platform Configuration37
General Routing Configuration Accesses38
- Standard PCI Bus Configuration Mechanism38
- Table 3-1. Device Number Assignment for Internal MCH Devices38
- Logical PCI Bus 0 Configuration Mechanism39
- Primary PCI and Downstream Configuration Mechanism39
- Figure 3-2. DMI Type 0 Configuration Address Translation39
- PCI Express* Enhanced Configuration Mechanism40
- Figure 3-3. DMI Type 1 Configuration Address Translation40
- Figure 3-4. Memory Map to PCI Express* Device Configuration Space41
- Figure 3-5. Intel41
- Intel 82925X/925XE MCH Configuration Cycle Flowchart42
I/O Mapped Registers43
- CONFIG_ADDRESS-Configuration Address Register43
- CONFIG_DATA-Configuration Data Register44
Table 4-1. Device 0 Function 0 Register Address Map Summary45
Host Bridge/Dram Controller Registers (D0:F0)45
Device 0 Function 0 PCI Configuration Register Details48
- VID-Vendor Identification (D0:F0)48
- DID-Device Identification (D0:F0)48
- PCICMD-PCI Command (D0:F0)49
- PCISTS-PCI Status (D0:F0)50
- RID-Revision Identification (D0:F0)51
- CC-Class Code (D0:F0)51
- MLT-Master Latency Timer (D0:F0)52
- HDR-Header Type (D0:F0)52
- SVID-Subsystem Vendor Identification (D0:F0)52
- SID-Subsystem Identification (D0:F0)53
- CAPPTR-Capabilities Pointer (D0:F0)53
- EPBAR-Egress Port Base Address (D0:F0)54
- MCHBAR-MCH Memory Mapped Register Range Base Address (D0:F0)55
- PCIEXBAR-PCI Express* Register Range Base Address (D0:F0)56
- DMIBAR-Root Complex Register Range Base Address (D0:F0)57
- DEVEN-Device Enable (D0:F0)58
- DEAP-DRAM Error Address Pointer (D0:F0) (Intel 82925X Only)59
- DERRSYN-DRAM Error Syndrome (D0:F0) (Intel 82925X Only)60
- DERRDST-DRAM Error Destination (D0:F0) (Intel61
- 82925X Only)61
- PAM0-Programmable Attribute Map 0 (D0:F0)62
- PAM1-Programmable Attribute Map 1 (D0:F0)63
- PAM2-Programmable Attribute Map 2 (D0:F0)64
- PAM3-Programmable Attribute Map 3 (D0:F0)65
- PAM4-Programmable Attribute Map 4 (D0:F0)66
- PAM5-Programmable Attribute Map 5 (D0:F0)67
- PAM6-Programmable Attribute Map 6 (D0:F0)68
- LAC-Legacy Access Control (D0:F0)69
- TOLUD-Top of Low Usable DRAM (D0:F0)70
- SMRAM-System Management RAM Control (D0:F0)71
- ESMRAMC-Extended System Management RAM Control (D0:F0)72
- ERRSTS-Error Status (D0:F0)72
- ERRCMD-Error Command (D0:F0)74
- SMICMD-SMI Command (D0:F0)75
- SCICMD-SCI Command (D0:F0)76
- SKPD-Scratchpad Data (D0:F0)76
- CAPID0-Capability Identifier (D0:F0)77
MCHBAR Registers79
MCHBAR Register Details80
- C0DRB0-Channel a DRAM Rank Boundary Address 080
- C0DRB1-Channel a DRAM Rank Boundary Address 182
- C0DRB2-Channel a DRAM Rank Boundary Address 282
- C0DRB3-Channel a DRAM Rank Boundary Address 382
- C0DRA0-Channel a DRAM Rank 0,1 Attribute83
- C0DRA2-Channel a DRAM Rank 2,3 Attribute83
- C0DCLKDIS-Channel a DRAM Clock Disable84
- C0BNKARC-Channel a DRAM Bank Architecture85
- C0DRT1-Channel a DRAM Timing Register86
- C0DRC0-Channel a DRAM Controller Mode 088
- C1DRB0-Channel B DRAM Rank Boundary Address 090
- C1DRB1-Channel B DRAM Rank Boundary Address 190
- C1DRB2-Channel B DRAM Rank Boundary Address 290
- C1DRB3-Channel B DRAM Rank Boundary Address 390
- C1DRA0-Channel B DRAM Rank 0,1 Attribute90
- C1DRA2-Channel B DRAM Rank 2,3 Attribute91
- C1DCLKDIS-Channel B DRAM Clock Disable91
- C1BNKARC-Channel B Bank Architecture91
- C1DRT1-Channel B DRAM Timing Register 191
- C1DRC0-Channel B DRAM Controller Mode 091
- PMCFG-Power Management Configuration92
- PMSTS-Power Management Status92
EPBAR Registers-Egress Port Register Summary93
EP RCRB Configuration Register Details93
- Figure 6-1. Link Declaration Topology93
- Table 6-1. Egress Port Register Address Map93
- EPESD-EP Element Self Description94
- EPLE1A-EP Link Entry 1 Address95
- EPLE1D-EP Link Entry 1 Description95
- EPLE2D-EP Link Entry 2 Description96
- EPLE2A-EP Link Entry 2 Address97
Table 7-1. DMI Register Address Map Summary99
DMIBAR Registers-Direct Media Interface (DMI) RCRB99
Direct Media Interface (DMI) RCRB Register Details100
- DMIVCECH-DMI Virtual Channel Enhanced Capability Header100
- DMIPVCCAP1-DMI Port VC Capability Register 1100
- DMIPVCCAP2-DMI Port VC Capability Register 2101
- DMIPVCCTL-DMI Port VC Control101
- DMIVC0RCAP-DMI VC0 Resource Capability102
- DMIVC0RCTL0-DMI VC0 Resource Control103
- DMIVC0RSTS-DMI VC0 Resource Status104
- DMIVC1RCAP-DMI VC1 Resource Capability104
- DMIVC1RCTL1-DMI VC1 Resource Control105
- DMIVC1RSTS-DMI VC1 Resource Status106
- DMILCAP-DMI Link Capabilities106
- DMILCTL-DMI Link Control107
- DMILSTS-DMI Link Status107
Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0)109
Host-PCI Express* Graphics Bridge Registers (D1:F0)109
Device 1 Configuration Register Details112
- VID1-Vendor Identification (D1:F0)112
- DID1-Device Identification (D1:F0)112
- PCICMD1-PCI Command (D1:F0)113
- PCISTS1-PCI Status (D1:F0)114
- RID1-Revision Identification (D1:F0)116
- CC1-Class Code (D1:F0)116
- CL1-Cache Line Size (D1:F0)117
- HDR1-Header Type (D1:F0)117
- PBUSN1-Primary Bus Number (D1:F0)117
- SBUSN1-Secondary Bus Number (D1:F0)118
- SUBUSN1-Subordinate Bus Number (D1:F0)118
- IOBASE1-I/O Base Address (D1:F0)119
- IOLIMIT1-I/O Limit Address (D1:F0)119
- SSTS1-Secondary Status (D1:F0)120
- MBASE1-Memory Base Address (D1:F0)121
- MLIMIT1-Memory Limit Address (D1:F0)122
- PMBASE1-Prefetchable Memory Base Address (D1:F0)123
- PMLIMIT1-Prefetchable Memory Limit Address (D1:F0)124
- CAPPTR1-Capabilities Pointer (D1:F0)124
- INTRLINE1-Interrupt Line (D1:F0)125
- INTRPIN1-Interrupt Pin (D1:F0)125
- BCTRL1-Bridge Control (D1:F0)126
- PM_CAPID1-Power Management Capabilities (D1:F0)128
- PM_CS1-Power Management Control/Status (D1:F0)129
- SS_CAPID-Subsystem ID and Vendor ID Capabilities (D1:F0)130
- SS-Subsystem ID and Subsystem Vendor ID (D1:F0)130
- MSI_CAPID-Message Signaled Interrupts Capability ID (D1:F0)131
- MC-Message Control (D1:F0)132
- MA-Message Address (D1:F0)133
- MD-Message Data (D1:F0)133
- PEG_CAPL-PCI Express* Capability List (D1:F0)134
- PEG_CAP-PCI Express*-G Capabilities (D1:F0)134
- DCAP-Device Capabilities (D1:F0)135
- DCTL-Device Control (D1:F0)136
- DSTS-Device Status (D1:F0)137
- LCAP-Link Capabilities (D1:F0)138
- LCTL-Link Control (D1:F0)139
- LSTS-Link Status (D1:F0)140
- SLOTCAP-Slot Capabilities (D1:F0)141
- SLOTCTL-Slot Control (D1:F0)142
- SLOTSTS-Slot Status (D1:F0)143
- RCTL-Root Control (D1:F0)144
- RSTS-Root Status (D1:F0)145
- PEGLC-PCI Express*-G Legacy Control146
- VCECH-Virtual Channel Enhanced Capability Header (D1:F0)147
- PVCCAP1-Port VC Capability Register 1 (D1:F0)147
- PVCCAP2-Port VC Capability Register 2 (D1:F0)148
- PVCCTL-Port VC Control (D1:F0)148
- VC0RCAP-VC0 Resource Capability (D1:F0)149
- VC0RCTL-VC0 Resource Control (D1:F0)149
- VC0RSTS-VC0 Resource Status (D1:F0)150
- VC1RCAP-VC1 Resource Capability (D1:F0)150
- VC1RCTL-VC1 Resource Control (D1:F0)151
- VC1RSTS-VC1 Resource Status (D1:F0)152
- RCLDECH-Root Complex Link Declaration Enhanced Capability Header (D1:F0)152
- ESD-Element Self Description (D1:F0)153
- LE1D-Link Entry 1 Description (D1:F0)154
- LE1A-Link Entry 1 Address (D1:F0)155
- PEGSSTS-PCI Express*-G Sequence Status (D1:F0)155
System Address Map157
- Figure 9-1. System Address Ranges158
- DOS Range (0H - 9_Ffffh)159
- Figure 9-2. Microsoft MS-DOS* Legacy Address Range159
- Legacy Video Area (A_0000H-B_Ffffh)159
- Expansion Area (C_0000H-D_Ffffh)160
- Table 9-1. Expansion Area Memory Segments160
- Extended System BIOS Area (E_0000H-E_Ffffh)161
- Programmable Attribute Map (PAM) Memory Area Details161
- System BIOS Area (F_0000H-F_Ffffh)161
- Table 9-2. Extended System BIOS Area Memory Segments161
- Table 9-3. System BIOS Area Memory Segments161
Legacy Address Range158
Main Memory Address Range (1 MB to TOLUD)162
- Figure 9-3. Main Memory Address Range162
- ISA Hole (15 MB-16 MB)162
- Pre-Allocated Memory163
- Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM and 1-MB TSEG163
- Tseg163
- APIC Configuration Space (Fec0_0000H-Fecf_Ffffh)164
- Figure 9-4. PCI Memory Address Range164
- HSEG (Feda_0000H-Fedb_Ffffh)165
- System Management Mode (SMM)167
PCI Memory Address Range (TOLUD - 4 GB)163
Functional Description173
- Host Interface173
- System Memory Controller174
- System Memory Configuration Register Overview176
- PCI Express182
- Power Management183
- Clocking183
- Figure 10-2. System Clocking Example184
Electrical Characteristics185
- Absolute Maximum Ratings185
- Table 11-1. Absolute Maximum Ratings185
- Power Characteristics186
- Figure 12-1. Intel186
- Table 11-2. Non-Memory Power Characteristics186
- Table 11-3. DDR2 Power Characteristics186
- Signal Groups187
- Table 11-4. Signal Groups187
- Figure 12-2. Intel188
- General DC Characteristics189
- Table 11-5. DC Characteristics189
Ballout and Package Information193
- Ballout193
  - Figure 12-1. Intel ® 82925X/82925XE MCH Ballout (Top View: Left Side)194
  - Figure 12-2. Intel ® 82925X/82925XE MCH Ballout (Top View: Right Side)195
- Table 12-1. MCH Ballout Sorted by Signal Name196
- Table 12-2. MCH Ballout Sorted by Ball Number207
- Package Information219
- Figure 12-3. MCH Package Dimensions220
Testability221
- Complimentary Pins221
- Table 13-1. Complimentary Pins to Drive221
- XOR Test Mode Initialization222
- XOR Chain Definition222
- XOR Chains222
- Table 13-2. XOR Chain Outputs222
- Table 13-3. XOR Chain #0223
- Table 13-4. XOR Chain #1225
- Table 13-5. XOR Chain #2227
- Table 13-6. XOR Chain #3229
- Table 13-7. XOR Chain #4231
- Table 13-8. XOR Chain #5233
- Table 13-9. XOR Chain #6235
- Table 13-10. XOR Chain #7237
- Table 13-11. XOR Chain #8239
- Table 13-12. XOR Chain #9241
- Pads Excluded from XOR Mode(S)242
- Table 13-13. XOR Pad Exclusion List242

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU

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