Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

System Address Map
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Intel
®
82925X/82925XE MCH Datasheet 169
9.4.4 SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows
software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit
to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM
mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI
Express. The SMM software can use this bit to write to video memory while running SMM code
out of DRAM.
Table 9-6. SMM Control Table
G_SMRAME D_LCK D_CLS D_OPEN CPU in
SMM Mode
SMM Code
Access
SMM Data
Access
0 x X x x Disable Disable
1 0 X 0 0 Disable Disable
1 0 0 0 1 Enable Enable
1 0 0 1 x Enable Enable
1 0 1 0 1 Enable Disable
1 0 1 1 x Invalid Invalid
1 1 X x 0 Disable Disable
1 1 0 x 1 Enable Enable
1 1 1 x 1 Enable Disable
9.4.5 SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
9.4.6 Processor WB Transaction to an Enabled SMM Address
Space
Processor write-back transactions (HREQ1# = 0) to enabled SMM address space must be written
to the associated SMM DRAM, even though the space is not open and the transaction is not
performed in SMM mode. This ensures SMM space cache coherency when cacheable extended
SMM space is used.

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English