Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
Intel
®
82925X/82925XE MCH Datasheet 107
7.1.12 DMILCTL—DMI Link Control
MMIO Range: DMIBAR
Address Offset: 088h
Default Value: 0000h
Access: R/W
Size: 16 bits
This register allows control of DMI.
Bit Access &
Default
Description
15:8 Reserved
7 R/W
0h
Extended Synch (ES):
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0 and extra TS1 sequences at exit from L1 prior to entering L0.
6:2 Reserved
1:0 R/W
00b
Active State Link PM Control (APMC): Indicates whether DMI should enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
7.1.13 DMILSTS—DMI Link Status
MMIO Range: DMIBAR
Address Offset: 08Ah
Default Value: 0001h
Access: RO
Size: 16 bits
This register indicates DMI status.
Bit Access &
Default
Description
15:10 Reserved
9:4 RO
00h
Negotiated Link Width (NLW): This field is valid only when the link is in the L0,
L0s, or L1 states (after link width negotiation is successfully completed).
Negotiated link width is x4 (000100b).
All other encodings are reserved.
3:0 RO
1h
Link Speed (LS)
Link is 2.5 Gb/s.
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Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English