Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 147
8.1.45 VCECH—Virtual Channel Enhanced Capability Header
(D1:F0)
PCI Device: 1
Address Offset: 100h
Default Value: 14010002h
Access: RO
Size: 32 bits
This register indicates PCI Express device Virtual Channel capabilities.
Note: Extended capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability structures.
Bit Access &
Default
Description
31:20 RO
140h
Pointer to Next Capability: The Link Declaration Capability is the next in the PCI
Express* extended capabilities list.
19:16 RO
1h
PCI Express Virtual Channel Capability Version: Hardwired to 1 to indicate
compliances with the 1.0a version of the PCI Express specification.
15:0 RO
0002h
Extended Capability ID: Value of 0002 h identifies this linked list item (capability
structure) as being for PCI Express Virtual Channel registers.
8.1.46 PVCCAP1—Port VC Capability Register 1 (D1:F0)
PCI Device: 1
Address Offset: 104h
Default Value: 00000001h
Access: RO, R/WO
Size: 32 bits
This register describes the configuration of PCI Express Virtual Channels associated with this
port.
Bit Access &
Default
Description
31:7 Reserved
6:4 RO
000b
Low Priority Extended VC Count: This field indicates the number of (extended)
Virtual Channels in addition to the default VC belonging to the low-priority VC
(LPVC) group that has the lowest priority with respect to other VC resources in a
strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
3 Reserved
2:0 R/WO
001b
Extended VC Count: This field indicates the number of (extended) Virtual
Channels in addition to the default VC supported by the device.
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