MCHBAR Registers
R
86 Intel
®
82925X/82925XE MCH Datasheet
5.1.9 C0DRT1—Channel A DRAM Timing Register
MMIO Range: MCHBAR
Address Offset: 114h
Default Value: 900122hh
Access: R/W, RO
Size: 32 bits
Bit Access &
Default
Description
31:24 Reserved
23:20 R/W
9h
Activate to Precharge delay (t
RAS
). This bit controls the number of DRAM clocks
for t
RAS
. Minimum recommendations are beside their corresponding encodings.
0h – 3h = Reserved
4h – Fh = Four to Fifteen Clocks respectively.
19 RO
0b
Reserved for Activate to Precharge Delay (t
RAS
) MAX: It is required that the
Panic Refresh timer be set to a value less than the t
RAS
maximum. Based on this
setting, a Panic Refresh occurs before T
RAS
maximum expiration and closes all
the banks.
This bit controls the maximum number of clocks that a DRAM bank can remain
open. After this time period, the DRAM controller will guarantee to pre-charge the
bank. This time period may or may not be set to overlap with time period that
requires a refresh to happen.
The DRAM controller includes a separate t
RAS-MAX
counter for every supported
bank. With a maximum of four ranks, and four banks per rank, there are 16
counters per channel.
0 = 120 microseconds
1 = Reserved
Note: This register will become Read Only with a value of 0 if the design does
not implement these counters.
t
RAS-MAX
is not required because a panic refresh will close all banks in a rank
before t
RAS-MAX
expires.
18:10 Reserved
9:8 R/W
01b
CASB Latency (tCL). This value is programmable on DDR2 DIMMs. The value
programmed here must match the CAS Latency of every DDR2 DIMM in the
system.
Encoding DDR2 CL
00 5
01 4
10 3
11 Reserved
7 Reserved
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