Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU - Page 87

MCHBAR Registers
R
Intel
®
82925X/82925XE MCH Datasheet 87
Bit Access &
Default
Description
6:4 R/W
010b
DRAM RAS to CAS Delay (t
RCD
). This bit controls the number of clocks inserted
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = Reserved
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
3 Reserved
2:0 R/W
010b
DRAM RAS Precharge (t
RP
). This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = Reserved
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved