Host-PCI Express* Graphics Bridge Registers (D1:F0)
R
134 Intel
®
82925X/82925XE MCH Datasheet
8.1.31 PEG_CAPL—PCI Express* Capability List (D1:F0)
PCI Device: 1
Address Offset: A0h
Default Value: 0010h
Access: RO
Size: 16 bits
This register enumerates the PCI Express capability structure.
Bit Access &
Default
Description
15:8 RO
00h
Pointer to Next Capability: This value terminates the capabilities list. The Virtual
Channel capability and any other PCI Express* specific capabilities that are
reported via this mechanism are in a separate capabilities list located entirely
within PCI Express extended configuration space.
7:0 RO
10h
Capability ID: This field identifies this linked list item (capability structure) as
being for PCI Express registers.
8.1.32 PEG_CAP—PCI Express*-G Capabilities (D1:F0)
PCI Device: 1
Address Offset: A2h
Default Value: 0141h
Access: RO
Size: 16 bits
This register indicates PCI Express device capabilities.
Bit Access &
Default
Description
15:14 Reserved
13:9 RO
00h
Interrupt Message Number: Hardwired to 0.
8 R/WO
1b
Slot Implemented
0 = The PCI Express* Link associated with this port is connected to an integrated
component or is disabled.
1 = The PCI Express Link associated with this port is connected to a slot.
BIOS must initialize this field appropriately if a slot connection is not implemented.
7:4 RO
4h
Device/Port Type: Hardwired to 0100 to indicate root port of PCI Express Root
Complex.
3:0 RO
1h
PCI Express Capability Version: Hardwired to 1 as it is the first version.