Functional Description
R
182 Intel
®
82925X/82925XE MCH Datasheet
10.4 PCI Express*
Refer to Chapter 1 for a list of PCI Express features, and the PCI Express specification for further
details.
The MCH is part of a PCI Express root complex. This means it connects a host processor/memory
subsystem to a PCI Express hierarchy.
The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model
(a load-store architecture with a flat address space) is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses standard
mechanisms as defined in the PCI Plug-and-Play specification. The initial speed of 1.25 GHz
(250 MHz internally) results in 2.5 Gb/s/direction that provides a 250 MB/s communications
channel in each direction (500 MB/s total) that is close to twice the data rate of classic PCI per
lane.
Note: The PCI Express graphics port will operate in x1 mode if a non-graphics card is plugged in.
10.4.1 Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer’s
primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
TLPs are used to communicate transactions (such as read and write as well as certain types of
events). The Transaction Layer also manages flow control of TLPs.
Note: If the MCH receives two back-to-back malformed packets, the second malformed packet is not
trapped or logged. The MCH will not log or identify the second malformed packet. However, the
1
st
malformed TLP is logged, and is considered a Fatal Error. Link behavior is not guaranteed at
that point whether a 2
nd
malformed TLP is detected or not.
10.4.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage
between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer
include link management, error detection, and error correction.
10.4.3 Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input
buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching
circuitry.
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