Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

Host Bridge/DRAM Controller Registers (D0:F0)
R
76 Intel
®
82925X/82925XE MCH Datasheet
4.1.34 SCICMD—SCI Command (D0:F0)
PCI Device: 0
Address Offset: CEh
Default Value: 0000h
Access: R/W
Size: 16 bits
This register enables various errors to generate an SMI DMI special cycle. When an error flag is
set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when
enabled in the ERRCMD, SMICMD, or SCICMD registers, respectively. Note that one and only
one message type can be enabled.
Bit Access &
Default
Description
15:2 Reserved
1 R/W 0b 82925X MCH
SCI on Multiple-Bit DRAM ECC Error (DMESCI):
1 = The MCH generates an SCI DMI message when it detects a multiple-bit error
reported by the DRAM controller.
0 = Reporting of this condition via SCI messaging is disabled. For systems not
supporting ECC this bit must be disabled.
82925XE MCH
Reserved
0 R/W 0b 82925X MCH
SCI on Single-bit ECC Error (DSESCI):
1 = The MCH generates an SCI DMI special cycle when the DRAM controller
detects a single bit error.
0 = Reporting of this condition via SCI messaging is disabled. For systems that do
not support ECC this bit must be disabled.
82925XE MCH
Reserved
4.1.35 SKPD—Scratchpad Data (D0:F0)
PCI Device: 0
Address Offset: DCh
Default Value: 00000000h
Access: R/W
Size: 32 bits
This register holds 32 writable bits with no functionality behind them. It is for the convenience of
BIOS and graphics drivers.
Bit Access &
Default
Description
31:0 R/W
00000000 h
Scratchpad Data: 1 DWord of data storage.

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English