Intel 80386 User Manual

PREFACE
• Chapter 4, "Performance Considerations." This chapter explores the factors that affect
the performance of an
80386 system.
o Chapter 5, "Coprocessor Hardware Interface." This chapter describes the interface
between the
80386 and the 80287 and 80387 Numeric Coprocessors. Each of these copro-
cessors expands the floating-point numerical processing capabilities of the
80386.
o Chapter 6, "Memory Interfacing." This chapter discusses techniques for designing memory
subsystems for the
80386.
•
Chapter 7, "Cache Subsystems." This chapter describes cache memory subsystems, which
provide higher performance at lower relative cost.
o Chapter 8, "I/O Interfacing." This chapter discusses techniques for connecting I/O devices
to an 80386 system.
• Chapter 9, "MULTIBUS® I and 80386." This chapter describes the interface between
an
80386 system and the Intel MUL TIBUS I multi-master system bus.
• Chapter 10, "MULTIBUS® II and 80386." This chapter describes the interface between
an
80386 system and the Intel MUL TIBUS II multi-master system bus.
o Chapter 11, "Physical Design and Debugging." This chapter contains recommendations
for constructing and debugging
80386 systems.
• Chapter 12, "Test Capabilities." This chapter describes 80386 test procedures.
o Appendix A contains descriptions of the components of the basic memory. interface
described
in Chapter 6.
• Appendix B contains descriptions of the components of the 80387 emulator described in
Chapter
5.
o Appendix C contains descriptions of the components of the dynamic RAM subsystem
described
in Chapter 6.
iv

Intel 80386 Specifications

General

Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Addressable Memory	4 GB
Data Bus Width	32-bit
Instruction Set	x86
Introduction Date	October 17, 1985
Virtual Memory	Yes
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Manufacturer	Intel
Model	80386
Address Bus Width	32-bit
Voltage	5V
Manufacturing Process	1.5 µm
Cache	No on-chip cache
FPU	Optional (80387)
Bus Interface	32-bit
Process Technology	CHMOS III
Package	PGA