Intel E6600 - Core 2 Duo Dual-Core Processor

Summary Tables of Changes
10 Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
AK = Intel
®
Core™2 Extreme quad-core processor QX6000 sequence and Intel
®
Core™2 Quad processor Q6 00 sequence
AL =
Dual-Core Intel
®
Xeon
®
processor 7100 series
AM =
Intel
®
Celeron
®
processor 400 sequence
AN = Intel
®
Pentium
®
dual-core processor
AO = Quad-Core Intel
®
Xeon
®
processor 3200 series
AP =
Dual-Core Intel
®
Xeon
®
processor 3000 series
AQ =
Intel
®
Pentium
®
dual-core desktop processor E2000 sequence
AR = Intel
®
Celeron
®
processor 500 series
AS = Intel
®
Xeon
®
processor 7200, 7300 series
AV = Intel
®
Core™2 Extreme processor QX9650 and Intel
®
Core™2 Quad processor
Q9000 series
AW =
Intel
®
Core™ 2 Duo processor E8000 series
AX =
Quad-Core Intel
®
Xeon
®
processor 5400 series
AY= Dual-Core Intel
®
Xeon
®
processor 5200 series
AZ = Intel
®
Core™2 Duo Processor and Intel
®
Core™2 Extreme Processor on 45-nm
Process
AAA =
Quad-Core Intel
®
Xeon
®
processor 3300 series
AAB =
Dual-Core Intel
®
Xeon
®
E3110 Processor
AAC = Intel
®
Celeron
®
dual-core processor E1000 series
AAD = Intel
®
Core™2 Extreme Processor QX9775Δ
AAE =
Intel
®
Atom™ processor Z5xx series
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and
other Intel products do not use this convention.
NO B1 B2 L2 M0 G0 Plan ERRATA
AI1 X X X X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AI2 X X X X X No Fix
LOCK# Asserted During a Special Cycle Shutdown Transaction
May Unexpectedly De-assert
AI3 X X X X X No Fix
Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
AI4 X X X X X No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update
the Last Exception Record (LER) MSR
AI5 X X X X X No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
AI6 X X X X Fixed
SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
AI7 X X X X X No Fix
General Protection Fault (#GP) for Instructions Greater than 15
Bytes May be Preempted
AI8 X X X X X No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
AI9 X X X X X No Fix The Processor May Report a #TS Instead of a #GP Fault