Intel E6600 - Core 2 Duo Dual-Core Processor

Summary Tables of Changes
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13
Specification Update
NO B1 B2 L2 M0 G0 Plan ERRATA
AI52 X X X X X No Fix
Last Branch Records (LBR) Updates May be Incorrect after a
Task Switch
AI53 X X X X X No Fix
IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
AI54 X X X X X No Fix INIT Does Not Clear Global Entries in the TLB
AI55 X X X X Fixed
Using Memory Type Aliasing with Memory Types WB/WT May
Lead to Unpredictable Behavior
AI56 X X X X Fixed
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause Unexpected
Processor Behavior
AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active
AI58 X X X X X No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater
or Equal to 2
48
May Terminate Early
AI59 X X X X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types may
use an Incorrect Data Size or Lead to Memory-Ordering
Violations.
AI60 X X X X X No Fix MOV To/From Debug Registers Causes Debug Exception
AI61 X X X X Fixed
Debug Register May Contain Incorrect Information on a MOVSS
or POPSS Instruction Followed by SYSRET
AI62 X X X X X No Fix
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
AI63 X X X X X No Fix
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AI64 X X X X X No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May
Result in Unpredictable System Behavior
AI65 X X X X X No Fix
A Thermal Interrupt is Not Generated when the Current
Temperature is Invalid
AI66 X X X X Fixed
VMLAUNCH/VMRESUME May Not Fail when VMCS is
Programmed to Cause VM Exit to Return to a Different Mode
AI67 X X X X X No Fix
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
AI68 X X X X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AI69 X X X X Fixed
CPL-Qualified BTS May Report Incorrect Branch-From
Instruction Address
AI70 X X X X Fixed
PEBS Does Not Always Differentiate Between CPL-Qualified
Events
AI71 X X X X X No Fix PMI May Be Delayed to Next PEBS Event
AI72 X X X X Fixed
PEBS Buffer Overflow Status Will Not be Indicated Unless
IA32_DEBUGCTL[12] is Set
AI73 X X X X X No Fix
The BS Flag in DR6 May be Set for Non-Single-Step #DB
Exception