Errata
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence 29
Specification Update
ordering issue if multiple loads access this shared data shortly thereafter.
Exposure to this problem requires the use of a data write which spans a
cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not
observed this erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying
shared data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent data
accesses.
Status: For the steppings affected, see the Summary Tables of Changes.
AI19. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the
code stream wraps around in a way that one instruction ends at the last byte
of the segment and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not
observed this erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
AI20. FP Inexact-Result Exception Flag May Not Be Set
Problem: When the result of a floating-point operation is not exactly representable in
the destination format (1/3 in binary form, for example), an inexact-result
(precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU
status word) is normally set by the processor. Under certain rare conditions,
this bit may not be set when this rounding occurs. However, other actions
taken by the processor (invoking the software exception handler if the
exception is unmasked) are not affected. This erratum can only occur if one
of the following FST instructions is one or two instructions after the floating-
point operation which causes the precision exception:
• FST m32real
• FST m64real
• FSTP m32real
• FSTP m64real
• FSTP m80real
• FIST m16int
• FIST m32int
• FISTP m16int
• FISTP m32int
• FISTP m64int
• FISTTP m16int
• FISTTP m32int
• FISTTP m64int
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