Intel E6600 - Core 2 Duo Dual-Core Processor User Manual

Errata
40 Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Implication: When the OS recovers from the second fault handler, the processor will no
longer be in VM86 mode. Normally, operating systems should prevent
interrupt task switches from faulting, thus the scenario should not occur
under normal circumstances.
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.
AI50. IA32_FMASK is Reset during an INIT
Problem: IA32_FMASK MSR (0xC0000084) is reset during INIT.
Implication: Implication: If an INIT takes place after IA32_FMASK is programmed, the
processor will overwrite the value back to the default value.
Workaround: Operating system software should initialize IA32_FMASK after INIT.
Status: For the steppings affected, see the Summary Tables of Changes.
AI51. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug
breakpoints until after execution of the following instruction. This is intended
to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP,
[r/e]BP instructions without having an invalid stack during interrupt handling.
However, an enabled debug breakpoint or single step trap may be taken after
MOV SS/POP SS if this instruction is followed by an instruction that signals a
floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This
results in a debug exception being signaled on an unexpected instruction
boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a
mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not
followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack
Segment and Stack Pointer on any exception. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: As recommended in the IA32 Intel
®
Architecture Software Developer’s
Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP
will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a
floating point exception. Developers of debug tools should be aware of the
potential incorrect debug event signaling created by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.

Intel E6600 - Core 2 Duo Dual-Core Processor Specifications

General

Processor Number	E6600
Number of Cores	2
Threads	2
Clock Speed	2.4 GHz
L2 Cache	4 MB
Bus Speed	1066 MHz
TDP	65 W
Socket	LGA 775
Lithography	65 nm
Max Operating Temperature	60.1°C
Instruction Set	64-bit
Release Date	Q3'06
Virtualization Technology	VT-x