Intel E6600 - Core 2 Duo Dual-Core Processor

Errata
48 Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
AI71. PMI May Be Delayed to Next PEBS Event
Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is
compared with the PEBS threshold, and the index is incremented with every
event. If PEBS index is equal to the PEBS threshold, a PMI (Performance
Monitoring Interrupt) should be issued. Due to this erratum, the PMI may be
delayed by one PEBS event.
Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence
by one PEBS event.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI72. PEBS Buffer Overflow Status Will Not be Indicated Unless
IA32_DEBUGCTL[12] is Set
Problem: IA32_PERF_GLOBAL_STATUS MSR (38EH) bit [62] when set, indicates that a
PEBS (Precise Event-Based Sampling) overflow has occurred and a PMI
(Performance Monitor Interrupt) has been sent. Due to this erratum, this bit
will not be set unless IA32_DEBUGCTL MSR (1D9H) bit [12] (which stops all
Performance Monitor Counters upon a PMI) is also set.
Implication: Unless IA32_DEBUGCTL[12] is set, IA32_PERF_GLOBAL_STATUS[62] will not
indicate that a PMI was generated due to a PEBS Overflow.
Workaround: It is possible for the software to set IA32_DEBUGCTL[12] to avoid this
erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AI73. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap
Flag, bit 8) of the EFLAGS Register is set, and a #DB (Debug Exception)
occurs due to one of the following:
• DR7 GD (General Detect, bit 13) being bit set;
• INT1 instruction;
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI74. An Asynchronous MCE During a Far Transfer May Corrupt ESP
Problem: If an asynchronous machine check occurs during an interrupt, call through
gate, FAR RET or IRET and in the presence of certain internal
conditions, ESP may be corrupted.