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Intel E6600 - Core 2 Duo Dual-Core Processor User Manual

Intel E6600 - Core 2 Duo Dual-Core Processor
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Errata
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence 55
Specification Update
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI94. Performance Monitoring Counter MACRO_INSTS.DECODED May Not
Count Some Decoded Instructions
Problem: MACRO_INSTS.DECODED performance monitoring counter (Event 0AAH,
Umask 01H) counts the number of macro instructions decoded, but not
necessarily retired. The event is undercounted when the decoded
instructions are a complete loop iteration that is decoded in one cycle and the
loop is streamed by the LSD (Loop Stream Detector), as described in the
Optimizing the Front End section of the Intel
®
64 and IA-32 Architectures
Optimization Reference Manual.
Implication: The count value returned by the performance monitoring counter
MACRO_INST.DECODED may be lower than expected. The degree of
undercounting is dependent on the occurrence of loop iterations that are
decoded in one cycle and whether the loop is streamed by the LSD while the
counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI95. The Stack Size May be Incorrect as a Result of VIP/VIF Check on
SYSEXIT and SYSRET
Problem: The stack size may be incorrect under the following scenario:
The stack size was changed due to a SYSEXIT or SYSRET
PVI (Protected Mode Virtual Interrupts) mode was enabled (CR4.PVI == 1)
Both the VIF (Virtual Interrupt Flag) and VIP (Virtual Interrupt Pending) flags of
the EFLAGS register are set
Implication: If this erratum occurs the stack size may be incorrect, consequently this may
result in unpredictable system behavior. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI96. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select
0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops
executed. The count for PMULUDQ micro-ops may be lower than expected.
No other instruction is affected.
Implication: The count value returned by the performance monitoring event
SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree of

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Intel E6600 - Core 2 Duo Dual-Core Processor Specifications

General IconGeneral
Processor NumberE6600
Number of Cores2
Threads2
Clock Speed2.4 GHz
L2 Cache4 MB
Bus Speed1066 MHz
TDP65 W
SocketLGA 775
Lithography65 nm
Max Operating Temperature60.1°C
Instruction Set64-bit
Release DateQ3'06
Virtualization TechnologyVT-x

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