Errata
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence 57
Specification Update
• One of the following simultaneous exception conditions is present following the
code transition
o Code #DB and code #PF
o Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code
Segment Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI100. Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating Frequency
Problem: Performance Counter MSR_PERF_FIXED_CTR2 (MSR 30BH) that counts
CPU_CLK_UNHALTED.REF clocks, should count these clock cycles at a
constant rate that is determined by the maximum resolved boot frequency,
as programmed by BIOS. Due to this erratum, the rate is instead set by the
maximum core-clock to bus-clock ratio of the processor, as indicated by
hardware.
Implication: No functional impact as a result of this erratum. If the maximum resolved
boot frequency as programmed by BIOS is different from the frequency
implied by the maximum core-clock to bus-clock ratio of the processor as
indicated by hardware, then the following effects may be observed:
• Performance Monitoring Event CPU_CLK_UNHALTED.REF will count at a rate
different than the TSC (Time Stamp Counter)
• When running a system with several processors that have different maximum
core-clock to bus-clock ratios, CPU_CLK_UNHALTED.REF monitoring events at
each processor will be counted at different rates and therefore will not be
comparable.
Workaround: Calculate the ratio of the rates at which the TSC and the
CPU_CLK_UNHALTED.REF performance monitoring event count (this can be
done by measuring simultaneously their counted value while executing code)
and adjust the CPU_CLK_UNHALTED.REF event count to the maximum
resolved boot frequency using this ratio.
Status: For the steppings affected, see the Summary Tables of Changes.
AI101. (E)CX May Get Incorrectly Updated When Performing Fast String REP
STOS With Large Data Structures
Problem: When performing Fast String REP STOS commands with data structures
[(E)CX*Data Size] larger than the supported address size structure (64K for
16-bit address size and 4G for 32-bit address size) some addresses may be
processed more than once. After an amount of data greater than or equal to
the address size structure has been processed, external events (such as
interrupts) will cause the (E)CX registers to be incremented by a value that
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