Intel E6600 - Core 2 Duo Dual-Core Processor User Manual

Errata
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence 65
Specification Update
AI120. VM Exit due to Virtual APIC-Access May Clear RF
Problem: RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart
instruction execution without getting an instruction breakpoint on the
instruction following a debug breakpoint exception. Due to this erratum, in a
system supporting Intel
®
Virtualization Technology, when a VM Exit occurs
due to Virtual APIC-Access (Advanced Programmable Interrupt Controller-
Access) the EFLAGS/RFLAGS saved in the VMCS (Virtual-Machine Control
Structure) may contain an RF value of 0.
Implication: When this erratum occurs, following a VM Exit due to a Virtual APIC-access,
the processor may unintentionally break on the subsequent instruction after
VM entry.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AI121. Fixed Function Performance Counters MSR_PERF_FIXED_CTR1
(30AH) and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When
the Processor is Reset
Problem: The Fixed Function Performance Counters that count the number of core
cycles and reference cycles when the core is not in a halt state are not
cleared when the processor is reset.
Implication: The MSR_PERF_FIXED_CTR1 and MSR_PERF_FIXED_CTR2 counters may
contain unexpected values after reset.
Workaround: BIOS can workaround this erratum by clearing the counters at processor
initialization time.
Status: For the steppings affected, see the Summary Tables of Changes.
AI122. VTPR Access May Lead to System Hang
Problem: The logical processor may hang if an instruction performs a VTPR access and
the next instruction to be executed is located on a different code page.
Implication: Software running VMX non-root operation may cause a logical processor to
hang if the virtual-machine monitor (VMM) sets both the "use TPR shadow"
and "virtualize APIC accesses" VM-execution controls.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AI123. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
Problem: IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to
indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at
the time of the last update to the IA32_MC1_STATUS MSR. Due to this

Intel E6600 - Core 2 Duo Dual-Core Processor Specifications

General

Processor Number	E6600
Number of Cores	2
Threads	2
Clock Speed	2.4 GHz
L2 Cache	4 MB
Bus Speed	1066 MHz
TDP	65 W
Socket	LGA 775
Lithography	65 nm
Max Operating Temperature	60.1°C
Instruction Set	64-bit
Release Date	Q3'06
Virtualization Technology	VT-x