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Specification Update
AAU39. DR6 May Contain Incorrect Information When the First Instruction
After a MOV SS,r/m or POP SS is a Store
Problem: Normally, each instruction clears the changes in DR6 (Debug Status Register) caused
by the previous instruction. However, the instruction following a MOV SS,r/m (MOV to
the stack segment selector) or POP SS (POP stack segment selector) instruction will not
clear the changes in DR6 because data breakpoints are not taken immediately after a
MOV SS,r/m or POP SS instruction. Due to this erratum, any DR6 changes caused by a
MOV SS,r/m or POP SS instruction may be cleared if the following instruction is a store.
Implication: When this erratum occurs, incorrect information may exist in DR6. This erratum will not
be observed under normal usage of the MOV SS,r/m or POP SS instructions (i.e.,
following them with an instruction that writes [e/r]SP). When debugging or when
developing debuggers, this behavior should be noted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU40. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also
Result in a System Hang
Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a
system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in
another machine check bank (IA32_MCi_STATUS).
Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang
and an Internal Timer Error to be logged.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU41. IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
Problem: The IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [34:32] may be incorrectly set to 7H
after reset; the correct value should be 0H.
Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset
(EN_FIXED_CTR{0, 1, 2} may be enabled).
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU42. Performance Monitor Counter INST_RETIRED.STORES May Count
Higher than Expected
Problem: Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track
retired instructions which contain a store operation. Due to this erratum, the processor
may also count other types of instructions including WRMSR and MFENCE.
Implication: Performance Monitoring counter INST_RETIRED.STORES may report counts higher than
expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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