Errata
Specification Update 23
AZ5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum the
memory page Access bit (A bit) may be set for the subsequent page prior to general
protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory and follows
a page that contains the code segment limit may be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable page)
as the last page of the segment or after the page that includes the code segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ6. Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the
following conditions are met:
Implication: A PDE (Page Directory Entry) is modified without invalidating the corresponding TLB
(Translation Look-aside Buffer) entry.
1. Code execution transitions to a different code page such that both
2. The target linear address corresponds to the modified PDE
3. The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit that
is clear
4. One of the following simultaneous exception conditions is present following the code
transition
5. Code #DB and code #PF
6. Code Segment Limit Violation #GP and code #PF
7. Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
To Next Page
Loading...
Need help?
General
