Errata
Specification Update 35
AZ35. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint
Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly
cleared when the following sequence happens:
1. POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint.
Implication: B0-B3 bits in DR6 may not be properly cleared.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AZ36. An xTPR Update Transaction Cycle, If Enabled, May Be Issued to the
FSB after the Processor has Issued a Stop-Grant Special Cycle
Problem: According to the FSB (Front Side Bus) protocol specification, no FSB cycles should be
issued by the processor once a Stop-Grant special cycle has been issued to the bus. If
xTPR update transactions are enabled by clearing the IA32_MISC_ENABLES[bit 23] at
the time of Stop-Clock assertion, an xTPR update transaction cycle may be issued to the
FSB after the processor has issued a Stop Grant Acknowledge transaction.
Implication: When this erratum occurs in systems using C-states C2 (Stop-Grant State) and higher
the result could be a system hang.
Workaround: BIOS must leave the xTPR update transactions disabled (default).
Status: For the steppings affected, see the Summary Tables of Changes.
AZ37. Performance Monitoring Event IA32_FIXED_CTR2 May Not Function
Properly When Max Ratio Is a Non-Integer Core-to-Bus Ratio
Problem: Performance Counter IA32_FIXED_CTR2 (MSR 30BH) event counts CPU reference clocks
when the core is not in a halt state. This event is not affected by core frequency changes
(e.g., P states, TM2 transitions) but counts at the same frequency as the Time-Stamp
Counter IA32_TIME_STAMP_COUNTER (MSR 10H). Due to this erratum, the
IA32_FIXED_CTR2 will not function properly when the non-integer core-to-bus ratio
multiplier feature is used and when a non-zero value is written to IA32_ FIXED_CTR2.
Non-integer core-to-bus ratio enables additional operating frequencies. This feature can
be detected by IA32_PLATFORM_ID (MSR 17H) bit [23].
Implication: The Performance Monitoring Event IA32_FIXED_CTR2 may result in an inaccurate count
when the non-integer core-to-bus multiplier feature is used.
Workaround: If writing to IA32_FIXED_CTR2 and using a non-integer core-to-bus ratio multiplier,
always write a zero.
Status: For the steppings affected, see the Summary Tables of Changes.
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