Errata
42 Specification Update
AZ51. LER MSRs May Be Incorrectly Updated
Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and
MSR_LER_TO_LIP (1DEH) may contain incorrect values after any of the following:
Either STPCLK#, NMI (NonMaskable Interrupt) or external interrupts
CMP or TEST instructions with an uncacheable memory operand followed by a
conditional jump
STI/POP SS/MOV SS instructions followed by CMP or TEST instructions and then by a
conditional jump
Implication: When the conditions for this erratum occur, the value of the LER MSRs may be
incorrectly updated.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
AZ52. Processor May Unexpectedly Assert False THERMTRIP# after Receiving
a Warm Reset
Problem: Some processors may unexpectedly assert a false THERMTRIP# after a warm reset under
certain environmental and operating conditions. Intel has observed this on a limited
number of parts when they are operating at a core-to-bus ratio different from the ratio
used at power-on. The issue is due to a thermal sensor circuit timing marginality event
that causes the sensor to initiate a thermal shutdown. Under these conditions, upon
RESET# assertion, some processors may assert a false THERMTRIP# even though their
temperature is below normal THERMTRIP# activation temperature. A warm reset is
different from a cold/power-on reset in that PWRGOOD remains active throughout the
assertion of RESET#.
Implication: This issue may be observed during warm reset cycle testing or during the process of
repeatedly entering and exiting the S3/S4/S5 sleep states. When this issue occurs, the
processor may proceed with a thermal shutdown signaled by the assertion of processor
THERMTRIP# and the platform will remove power from the CPU or the entire platform.
Workaround: A BIOS update can be implemented to address this erratum. The workaround found in
the BIOS requires that the processor transition to Low Frequency mode before a warm
reset. Please contact your local Intel representative for more information.
Note: This workaround does not cover all system configurations where warm resets are
initiated by Intel® AMT.
Status: For the steppings affected, see the Summary Tables of Changes.
To Next Page
Loading...
