Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile CPU - Identification Information; Component Identification via Programming Interface

Identification Information
Specification Update 7
Identification Information
Component Identification via Programming Interface
Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile
Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile
Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45-
nm Process stepping can be identified by the following register contents:
Reserved
Extended
Family
1
Extended
Model
2
Reserved
Processor
Type
3
Family
Code
4
Model
Number
5
Stepping
ID
6
31:28
27:20
19:16
15:14
13:12
11:8
7:4
3:0
0000000b
0001b
00b
0110b
0111b
XXXXb
When EAX is initialized to a value of 1, the CPUID instruction returns the Extended
Family, Extended Model, Type, Family, Model and Stepping value in the EAX register.
Note that the EDX processor signature value after reset is equivalent to the processor
signature output value in the EAX register.
NOTES:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in
bits [11:8], to indicate whether the processor belongs to the Intel386®, Intel486®,
Pentium®, Pentium Pro, Pentium 4, or Intel Core processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits
[7:4], are used to identify the model of the processor within the processor‟s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original
OEM processor, an OverDrive processor, or a dual processor (capable of being used in a dual
processor system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
generation field of the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
model field of the Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 2 for the
processor stepping ID number in the CPUID information.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.