The Zilog Z80 CPU is a fourth-generation enhanced microprocessor designed for high system throughput and efficient memory utilization. It operates with a single +5V power source and offers speed options from 6 MHz to 20 MHz, making it suitable for a wide range of applications. The CPU's internal architecture includes 208 bits of read/write memory accessible to the programmer, comprising eighteen 8-bit registers and four 16-bit registers. These include two sets of six general-purpose registers (BC, DE, HL and BC', DE', HL') that can be used individually as 8-bit registers or in pairs as 16-bit registers, along with two sets of Accumulator and Flag registers.
Key Registers and Their Functions:
- Program Counter (PC): A 16-bit register that holds the address of the current instruction being fetched. It increments automatically after its contents are transferred to the address lines. Jumps load a new value into the PC.
- Stack Pointer (SP): A 16-bit register pointing to the top of an external LIFO stack in RAM. It facilitates multiple-level interrupts, subroutine nesting, and data manipulation through PUSH and POP instructions.
- Index Registers (IX and IY): Two independent 16-bit registers used as base addresses in indexed addressing modes. An additional byte in indexed instructions specifies a two's complement signed integer displacement from this base, simplifying table-based data access.
- Interrupt Page Address (I) Register: Stores the high-order eight bits of an indirect address for interrupt responses in Mode 2. The interrupting device provides the lower eight bits, allowing dynamic location of interrupt routines.
- Memory Refresh (R) Register: An 8-bit register with seven bits automatically incremented after each instruction fetch, enabling dynamic memory refresh transparently to the programmer. The eighth bit is programmed via an LD R, A instruction. During refresh, I Register contents are placed on the upper eight bits of the address bus.
- Accumulator and Flag Registers (AF, AF'): Two independent 8-bit Accumulators hold results of 8-bit arithmetic/logical operations. Associated 8-bit Flag Registers indicate conditions for 8-bit or 16-bit operations (e.g., zero result). A single exchange instruction allows switching between the two AF pairs.
Arithmetic Logic Unit (ALU) Functions:
The 8-bit arithmetic and logical instructions are executed in the ALU, which communicates with registers and the external data bus. Functions include:
- Add, Subtract
- Logical AND, OR, XOR
- Compare
- Left/right shifts or rotates (arithmetic and logical)
- Increment, Decrement
- Set, Reset, Test bits
Pin Functions:
The Z80 CPU features a 16-bit Address Bus (A15–A0) for memory (up to 64 KB) and I/O exchanges. The Data Bus (D7–D0) is an 8-bit bidirectional bus. Control signals include:
- BUSACK (Bus Acknowledge): Active Low output, indicates CPU address/data/control lines (MREQ, IORQ, RD, WR) are in high-impedance state, allowing external devices to control them. Has higher priority than NMI.
- BUSREQ (Bus Request): Active Low input, recognized at the end of the current machine cycle. Forces CPU buses to high-impedance.
- HALT (HALT State): Active Low output, indicates CPU executed HALT and waits for interrupt. CPU executes NOPs to maintain memory refresh during HALT.
- INT (Interrupt Request): Active Low input from I/O devices. Honored if interrupt enable flip-flop (IFF) is enabled.
- IORQ (Input/Output Request): Active Low, tristate output. Indicates valid I/O address on lower address bus or interrupt acknowledge cycle.
- M1 (Machine Cycle One): Active Low output. With MREQ, indicates op code fetch. With IORQ, indicates interrupt acknowledge.
- MREQ (Memory Request): Active Low, tristate output. Indicates valid address on bus for memory read/write.
- NMI (Nonmaskable Interrupt): Negative edge-triggered input. Higher priority than INT, forces CPU to restart at 0066h. Cannot be disabled by software.
- RD (Read): Active Low, tristate output. Indicates CPU wants to read data from memory/I/O.
- RESET (Reset): Active Low input. Initializes CPU: resets IFF, clears PC and I/R registers, sets interrupt status to Mode 0. Address/data bus enter high-impedance, control outputs inactive. Must be active for 3 clock cycles.
- RFSH (Refresh): Active Low output. With MREQ, indicates lower seven bits of address bus are refresh address for dynamic memories.
- WAIT (WAIT): Active Low input. Communicates memory/I/O not ready for data transfer. CPU enters WAIT state as long as active.
Timing and Operations:
The Z80 CPU executes instructions through a series of machine (M) cycles, each consisting of time (T) cycles.
- Instruction Fetch (M1): Program Counter on address bus, MREQ and RD active. Data sampled on rising edge of T3. T3 and T4 used for dynamic memory refresh (RFSH active, lower seven address bits are refresh address).
- Memory Read/Write: Generally three T cycles. MREQ and RD/WR signals active when address/data bus stable. WR signal goes inactive before address/data change.
- Input/Output Cycles: Automatically inserts one wait state to allow I/O port address decoding and WAIT signal activation. RD enables data onto bus for reads, WR clocks data for writes.
- Bus Request/Acknowledge: BUSREQ sampled on rising edge of last clock period. CPU sets address/data/tristate control signals to high-impedance on next rising clock edge. External device controls buses.
- Interrupt Request/Acknowledge: INT sampled on rising edge of final clock. If accepted, special M1 cycle generated, IORQ active. Two wait states automatically added for ripple priority interrupt scheme.
- Nonmaskable Interrupt Response: NMI sampled same time as INT, but takes priority. CPU ignores data bus contents, stores PC in external stack, jumps to 0066h.
- HALT Exit: Exits HALT state on next rising clock edge after NMI or maskable interrupt (if enabled). Executes NOPs in HALT to maintain refresh.
- Power-Down Acknowledge/Release: CPU stops operation when clock input stopped (High/Low). ICC2 guaranteed when clock stopped Low during T4 after HALT. System clock must be supplied to release power-down. Interrupt (NMI/INT) or RESET required to exit power-down.
Interrupt Response Modes:
- Mode 0 (8080A compatible): Interrupting device places any instruction on data bus for CPU execution. Often a single-byte restart instruction. Two extra clock cycles added for external daisy-chain priority control.
- Mode 1: CPU executes restart at 0038h. Identical to NMI response except for call location. Two extra clock cycles added.
- Mode 2 (Vectored Interrupt): Most powerful. CPU forms 16-bit indirect pointer from I Register (high-order 8 bits) and 8-bit vector from peripheral (lower 8 bits, LSB is 0). This pointer addresses a table of 16-bit service routine starting addresses. CPU pushes PC onto stack, obtains address from table, and jumps. Requires 19 clock periods.
Instruction Set Overview:
The Z80 CPU supports 158 instruction types, including all 78 of the 8080A CPU. Major groups include:
- Load and Exchange: Move data between registers, memory, or exchange register contents. Block transfer instructions move large data strings efficiently.
- Arithmetic and Logical: 8-bit and 16-bit operations on Accumulator, general-purpose registers, or memory. Includes DAA for BCD arithmetic.
- Rotate and Shift: Rotate/shift data in Accumulator, general-purpose registers, or memory (left/right, with/without carry, arithmetic/logical). RRD/RLD rotate Accumulator digits with memory digits for BCD arithmetic.
- Bit Manipulation: Set, reset, or test any bit in Accumulator, general-purpose registers, or memory.
- Jump, Call, and Return: Transfer program control. Includes RESTART (single-byte call to page 0 addresses) and conditional jumps/calls/returns based on Flag Register status.
- Input/Output: Transfer data between memory/registers and I/O devices. Supports absolute or Register Indirect addressing (using C register for port address, B register for upper address bits). Includes block I/O transfer instructions.
- Basic CPU Control: HALT, DI (Disable Interrupt), EI (Enable Interrupt), IM (Interrupt Mode) commands, NOP.
Addressing Modes:
- Immediate: Operand is the byte(s) immediately following the op code.
- Modified Page Zero: Single-byte CALL instruction to one of eight fixed locations in Page 0 of memory (restarts).
- Relative: One byte displacement added to PC for jumps, allowing relocatable code and saving memory space.
- Extended: Two bytes (16 bits) of address included in instruction for jumps or operand location.
- Indexed: Displacement added to IX or IY register to form memory pointer.
- Register: Op code bits specify which CPU register to use.
- Implied: Op code automatically implies one or more CPU registers as operands.
- Register Indirect: 16-bit CPU register pair (e.g., HL) used as memory pointer.
The Z80 CPU is designed for ease of integration into systems, with fully decoded and timed output signals for standard memory and peripheral circuits.
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