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JRC JRL-2000F - Page 17

JRC JRL-2000F
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IC3 is a memory
IC
which supports electrical write/erase, and the tuning date of each
band is stored in it. Switch
S1
provides initial conditions to the CPU
of
the JRL-2000F.
IC2, TR3, TR4, S2 and peripheral parts compose of a CPU reset circuit, and IC2
detects the drop of the CPU operatingvaltage DC 5V.
(2)Description of 1/0 Signals
Refer to the instructions manual for the connecting signals with the exciter.
Signalname
1/0 Description
PSALM
Input
Alarm from NBL-169
VPA ON RESP Input
Response of PA power supply valtage
VPA ON CONT Output
Truns on CBG-68
---
Truns on the relay which provides
MAINON
Output
NBL-169 with AC power supply
K1
Output
Truns on
K1
of CSC-433
.K2
Output Truns on
K2
of CSC-433
K3
Output Truns on K3 of CSC-433
ANT1
Output Truns on ANT1 of CSC-433
ANT2 Output
Truns on ANT2 of CSC-433
ANT3 Output
Truns on ANT3 of CSC-433
ANT4
Output
Truns on ANT4
of
CSC-433
S-DATA Output
Sends data to the
relay.
IC
of CFG-111
LATCH Output
Latches S-DAT A signal
in
the
IC
memory
ENABLE Output
Enable output of the relay drive
IC
of CFG-111
K4
Output Truns on relays
in
CFF-361
PA KEY
ON
Output
Truns on PA bias circuit
PA OFF Output
Truns PA bias voltage to minus voltage
PA HEAT Input
Alarm for overheat of PA heat sink
PA BL Input
Alarm for PA unbalanced
PA LOAD Input
Alarm for PA abnormal Ioad impedance
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