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JRC JRL-2000F - 5.2 Rear Panel Controls

JRC JRL-2000F
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The exciter enters transmit state and the LED of XMT on the front panellights up for
as long as the signalline of No.11 pin (SELBK)
of
J3
is correctly connected to the
exiter. The power from the exciter is divided
by
R1
and R2
of
the CSC-433 antenna
switch circuit and
R61
of the CDJ-1143 control.circuit, and the frequency of the signal
is measured.
Refer to "2.6 CDJ-1143 control (4)" for the frequency measurement.
IC16 of CDJ-1143 coritrol circuit checks the divided signal Ievei and if the input power
is too small (below about 20 W), No.7 pin
of
IC16 changes to High Ievei.
lf
it is too
large (over about 150 W),
No.1
pin
ofiC16
changes to Low Ievei. CPU checks the
state of the signal at times and displays Po
with
the seven-segment LED on the front
panel
when
the input is too small, and
AG
when it is too large. After frequency mea-
surement is completed, the data of EEPROM is checked in relation with the obtained
frequency. ln EEPROM, the data is memorized in a matrix as shown in Fig.9. For
example, assume that the frequency is 14.020MHz. As the related data exists in the
No.2 antenna column, the antenna circuit is switched to No.2 antenna and relays
of
the CFG-111 matehing circuit are preset according to the data. The frequency display
is also switched. ln addition, the antenna number last used is stored in RAM incorpo-
rated in CPU and it will be selected if two or more data exist for one frequency.
The data capacity
of
30-bit is required for one cell because there are 30 relays in
CFG-111 matehing circuit and one more bit is added to indicate that there
is
data
or
not. The bit is set to "no data" for all cells on shipping. When the automatic tuning is
completed, the bit changes to "data exists" state. As the 8-bit/1 word EEPROM is used
here, four words will be assigned to a matrix.
Antenna number
Freguency
1
2
3
I
.600-
I
.6
IOMHz
FFFFFFFF
FFFFFFFF
FFFFFFFF
14.000-14.080MHz
FFFFFFFF
0543F2D6
FFFFFFFF
'
29.900-
30.000MHz
FFFFFFFF
FFFFFFFF
FFFFFFFF
All the data is set to FFFFFFFF on shipping.
Fig. 9 Memory Map
18
4
FFFFFFFF
FFFFFFFF
FFFFFFFF
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